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path: root/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
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* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-8/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+6
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-5/+0
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-15/+21
| | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. llvm-svn: 75359
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75036
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-0/+55
| | | | | | shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-0/+304
Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
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