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path: root/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
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* Don't attempt preserving conservative kill flags. We were doing it wrong.Jakob Stoklund Olesen2010-06-161-2/+1
| | | | | | This is before LiveVariables anyway, where these kill flags are recalculated. llvm-svn: 106157
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-2/+1
| | | | | | now, so there's no need to disable them. llvm-svn: 106155
* Fix up a comment.Bob Wilson2010-06-081-2/+2
| | | | llvm-svn: 105591
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-6/+6
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng2010-05-141-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. llvm-svn: 103835
* Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.Evan Cheng2010-05-141-10/+29
| | | | llvm-svn: 103790
* Fix -Asserts warning.Daniel Dunbar2010-05-131-0/+1
| | | | llvm-svn: 103694
* vst instructions are modeled as this:Evan Cheng2010-05-121-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | v1024 = REG_SEQUENCE ... v1025 = EXTRACT_SUBREG v1024, 5 v1026 = EXTRACR_SUBREG v1024, 6 = VSTxx <addr>, v1025, v1026 The REG_SEQUENCE ensures the sources that feed into the VST instruction are getting the right register allocation so they form a large super- register. The extract_subreg will be coalesced away all would just work: v1024 = REG_SEQUENCE ... = VSTxx <addr>, v1024:5, v1024:6 The problem is if the coalescer isn't run, the extract_subreg instructions would stick around and there is no assurance v1025 and v1026 will get the right registers. As a short term workaround, teach the NEON pre-allocation pass to transfer the sub-register indices over. An alternative would be do it 2addr pass when reg_sequence's are eliminated. But that *seems* wrong and require updating liveness information. Another alternative is to do this in the scheduler when the instructions are created. But that would mean somehow the scheduler this has to be done for correctness reason. That's yucky as well. So for now, we are leaving this in the target specific pass. llvm-svn: 103540
* Avoid breaking vstd when reg_sequence is not used.Evan Cheng2010-05-111-1/+2
| | | | llvm-svn: 103513
* Model some vst3 and vst4 with reg_sequence.Evan Cheng2010-05-111-6/+10
| | | | llvm-svn: 103453
* Model some vld3 instructions with REG_SEQUENCE.Evan Cheng2010-05-101-29/+53
| | | | llvm-svn: 103437
* Model vld2 / vst2 with reg_sequence.Evan Cheng2010-05-101-3/+6
| | | | llvm-svn: 103411
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Do not pre-allocate references of D registers pairs if they are extracted ↵Evan Cheng2010-05-051-8/+28
| | | | | | from the same Q register and are in the right order. llvm-svn: 103124
* Do not pre-allocate for registers which form a REG_SEQUENCE.Evan Cheng2010-05-041-0/+28
| | | | llvm-svn: 103041
* Change VST1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-5/+4
| | | | | | | of D registers. Add a separate VST1q instruction with a Q register source operand for use by storeRegToStackSlot. llvm-svn: 99265
* Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-1/+8
| | | | | | | of D registers. Add a separate VLD1q instruction with a Q register destination operand for use by loadRegFromStackSlot. llvm-svn: 99261
* Rename some VLD1/VST1 instructions to match the implementation, i.e., theBob Wilson2010-03-221-4/+4
| | | | | | | corresponding NEON instructions, instead of operation they are currently used for. llvm-svn: 99189
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-14/+14
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* Rename some instructions for consistency and sanity: use "_UPD" suffix forBob Wilson2010-03-201-48/+48
| | | | | | | | load/stores with address register writeback, and use "odd" suffix to distinguish instructions to access odd numbered registers (instead of "a" and "b"). No functional changes. llvm-svn: 99066
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-14/+14
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-14/+14
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Support alignment specifier for NEON vld/vst instructionsJim Grosbach2009-11-071-14/+14
| | | | llvm-svn: 86404
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-091-0/+16
| | | | llvm-svn: 83600
* Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+16
| | | | llvm-svn: 83598
* Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+16
| | | | llvm-svn: 83596
* Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+16
| | | | | | Also fix some copy-and-paste errors in previous changes. llvm-svn: 83590
* Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-7/+23
| | | | llvm-svn: 83585
* Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+16
| | | | llvm-svn: 83568
* Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83526
* Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83518
* Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83513
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83508
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83506
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83502
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+18
| | | | llvm-svn: 83486
* Add codegen support for NEON vst3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+18
| | | | llvm-svn: 83484
* Add codegen support for NEON vst2 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+7
| | | | llvm-svn: 83482
* Add codegen support for NEON vld4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+18
| | | | llvm-svn: 83479
* Add codegen support for NEON vld3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-6/+29
| | | | llvm-svn: 83471
* Add codegen support for NEON vld2 operations on quad registers.Bob Wilson2009-10-061-0/+7
| | | | llvm-svn: 83422
* Use copyRegToReg hook to copy registers.Bob Wilson2009-10-061-6/+4
| | | | llvm-svn: 83421
* Add support for generating code for vst{234}lane intrinsics.Bob Wilson2009-09-011-0/+9
| | | | llvm-svn: 80707
* Generate code for vld{234}_lane intrinsics.Bob Wilson2009-09-011-0/+9
| | | | llvm-svn: 80656
* Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.Bob Wilson2009-08-121-0/+30
| | | | llvm-svn: 78835
* Implement Neon VST[234] operations.Bob Wilson2009-08-061-0/+21
| | | | llvm-svn: 78330
* Neon does not actually have VLD{234}.64 instructions.Bob Wilson2009-08-061-3/+0
| | | | | | These operations will have to be synthesized from other instructions. llvm-svn: 78263
* Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson2009-08-051-0/+137
that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. llvm-svn: 78256
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