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* [MC] Plumb unique_ptr<MCMachObjectTargetWriter> through createMachObjectWriterLang Hames2017-10-091-4/+3
| | | | | | | | | | | to MCObjectWriter's constructor. MCObjectWriter takes ownership of its MCMachObjectTargetWriter argument -- this patch plumbs that ownership relationship through the constructor (which previously took raw MCMachObjectTargetWriter*) and the createMachObjectWriter function. llvm-svn: 315245
* [ARM] v8.3-a complex number supportSam Parker2017-09-291-0/+1
| | | | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511
* Fix ARMv4 supportJoerg Sonnenberger2017-08-281-2/+2
| | | | | | | | | | | | | | | | | | ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
* [ARM] Tidy-up condition-code support functionsJaved Absar2017-08-271-64/+1
| | | | | | | | | Move condition code support functions to Utils and remove code duplication. Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37179 llvm-svn: 311860
* ARM: use internal relocations for local symbols after all.Tim Northover2017-08-231-2/+11
| | | | | | | | | | | Switching to external relocations for ARM-mode branches (to allow Thumb interworking when the offset is unencodable) causes calls to temporary symbols to be miscompiled and instead go to the parent externally visible symbol. Calling a temporary never happens in compiled code, but can occasionally in hand-written assembly. llvm-svn: 311611
* ARM: use an external relocation for calls from MachO ARM mode.Tim Northover2017-08-181-5/+4
| | | | | | | The internal (__text-relative) relocation risks the offset not being encodable if the destination is Thumb. llvm-svn: 311187
* [Triple] Add isThumb and isARM functions.Florian Hahn2017-08-121-4/+1
| | | | | | | | | | | | | | | | | | | Summary: isThumb returns true for Thumb triples (little and big endian), isARM returns true for ARM triples (little and big endian). There are a few more checks using arm/thumb that are not covered by those functions, e.g. that the architecture is either ARM or Thumb (little endian) or ARM/Thumb little endian only. Reviewers: javed.absar, rengolin, kristof.beyls, t.p.northover Reviewed By: rengolin Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D34682 llvm-svn: 310781
* [TargetParser] Use enum classes for various ARM kind enums.Florian Hahn2017-07-274-53/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Using c++11 enum classes ensures that only valid enum values are used for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the need for checks that the provided values map to a proper enum value, allows us to get rid of AK_LAST and prevents comparing values from different enums. It also removes a bunch of static_cast from unsigned to enum values and vice versa, at the cost of introducing static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind. FPUKind and ArchExtKind are the only remaining old-style enum in TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style enum, but FPUKind can be converted too, but this patch is quite big, so could do this in a follow-up patch. I could also split this patch up a bit, if people would prefer that. Reviewers: rengolin, javed.absar, chandlerc, rovka Reviewed By: rovka Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35882 llvm-svn: 309287
* Simplify. NFC.Rafael Espindola2017-07-261-176/+114
| | | | llvm-svn: 309141
* Remove Bitrig: LLVM ChangesErich Keane2017-07-211-1/+0
| | | | | | | | Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned. Differential Revision: https://reviews.llvm.org/D35707 llvm-svn: 308799
* Fully fix the movw/movt addend.Rafael Espindola2017-07-112-12/+11
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
* Rename and adjust processFixupValue.Rafael Espindola2017-06-302-12/+11
| | | | | | | It was not processing any value. All that it ever did was force relocations, so name it shouldForceRelocation. llvm-svn: 306906
* Don't repeat names and reformat. NFC.Rafael Espindola2017-06-281-46/+37
| | | | llvm-svn: 306556
* Simplify the processFixupValue interface. NFC.Rafael Espindola2017-06-242-8/+3
| | | | llvm-svn: 306202
* Remove redundant argument.Rafael Espindola2017-06-242-2/+3
| | | | llvm-svn: 306189
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-232-23/+35
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* COFF: Produce an error on invalid pcrel relocs.Rafael Espindola2017-06-231-3/+4
| | | | | | | | | | X86_64 COFF only has support for 32 bit pcrel relocations. Produce an error on all others. Note that gnu as has extended the relocation values to support this. It is not clear if we should support the gnu extension. llvm-svn: 306082
* [ARM] Create relocations for beq.w branches to ARM function syms.Florian Hahn2017-06-221-0/+1
| | | | | | | | | | | | | | | | | | Summary: The ARM ELF ABI requires the linker to do interworking for wide conditional branches from Thumb code to ARM code. That was pointed out by @peter.smith in the comments for D33436. Reviewers: rafael, peter.smith, echristo Reviewed By: peter.smith Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith Differential Revision: https://reviews.llvm.org/D34447 llvm-svn: 306009
* Use a MutableArrayRef. NFC.Rafael Espindola2017-06-212-5/+5
| | | | llvm-svn: 305968
* [ARM] Use FixupKind variable in processFixupValue (cleanup, NFC).Florian Hahn2017-06-071-10/+10
| | | | llvm-svn: 304905
* [ARM] Create relocations for unconditional branches.Florian Hahn2017-06-071-7/+12
| | | | | | | | | | | | | | | | | | | Summary: Relocations are required for unconditional branches to function symbols with different execution mode. Without this patch, incorrect branches are generated for tail calls between functions with different execution mode. Reviewers: peter.smith, rafael, echristo, kristof.beyls Reviewed By: peter.smith Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33898 llvm-svn: 304882
* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-076-7/+7
| | | | | | | | | | | | This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-065-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [ARM] Add curly braces around switch case [NFC] Peter Smith2017-06-061-1/+2
| | | | | | | | | | | | | My previous commit r304702 introduced a new case into a switch statement. This case defined a variable but I forgot to add the curly brackets around the case to limit the scope. This change puts the curly braces back in so that the next person that adds a case doesn't get a build failure. Thanks to avieira for the spot. Differential Revision: https://reviews.llvm.org/D33931 llvm-svn: 304785
* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-053-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [ARM] Create relocations for Thumb functions calling ARM fns in ELF.Florian Hahn2017-06-011-0/+9
| | | | | | | | | | | | | | | | Summary: Without using a fixup in this case, BL will be used instead of BLX to call internal ARM functions from Thumb functions. Reviewers: rafael, t.p.northover, peter.smith, kristof.beyls Reviewed By: peter.smith Subscribers: srhines, echristo, aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33436 llvm-svn: 304413
* Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg ↵James Molloy2017-05-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | directives Re-applying now that PR32825 which was raised on the commit this fixed up is now known to have also been fixed by this commit. Original commit message: Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 303540
* Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives"James Molloy2017-05-221-1/+0
| | | | | | | | This reverts commit r302416. This was a fixup for r286006, which has now been reverted so this doesn't apply (either in concept or in code). This commit itself has no problems, but the underlying issue it was fixing has now disappeared from the codebase. llvm-svn: 303536
* [ARM] Clear the constant pool cache on explicit .ltorg directivesMartin Storsjo2017-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 302416
* [ARM] Fix handling of mapping symbols when changing sectionsJohn Brawn2017-04-201-1/+1
| | | | | | | | | | | ChangeSection incorrectly registers LastEMSInfo as belonging to the previous section, not the current section. This happens to work when changing sections using .section, as the previous section is set to the current section before the call to ChangeSection, but not when using .popsection. Differential Revision: https://reviews.llvm.org/D32225 llvm-svn: 300831
* [ARM] Rename HW div feature to HW div Thumb. NFCI.Diana Picus2017-04-201-2/+2
| | | | | | | | | | | | | | | | The hardware div feature refers only to Thumb, but because of its name it is tempting to use it to check for hardware division in general, which may cause problems in ARM mode. See https://reviews.llvm.org/D32005. This patch adds "Thumb" to its name, to make its scope clear. One notable place where I haven't made the change is in the feature flag (used with -mattr), which is still hwdiv. Changing it would also require changes in a lot of tests, including clang tests, and it doesn't seem like it's worth the effort. Differential Revision: https://reviews.llvm.org/D32160 llvm-svn: 300827
* [ARM] Add hardware build attributes in assemblerOliver Stannard2017-04-181-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the assembler, we should emit build attributes based on the target selected with command-line options. This matches the GNU assembler's behaviour. We only do this for build attributes which describe the hardware that is expected to be available, not the ones that describe ABI compatibility. This is done by moving some of the attribute emission code to ARMTargetStreamer, so that it can be shared between the assembly and code-generation code paths. Since the assembler only creates a MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to check raw features, and not use the convenience functions in ARMSubtarget. If different attributes are later specified using the .eabi_attribute directive, then they will take precedence, as happens when the same .eabi_attribute is specified twice. This must be enabled by an option, because we don't want to do this when parsing inline assembly. The attributes would match the ones emitted at the start of the file, so wouldn't actually change the emitted object file, but the extra directives would be added to every inline assembly block when emitting assembly, which we'd like to avoid. The majority of the changes in the build-attributes.ll test are just re-ordering the directives, because the hardware attributes are now emitted before the ABI ones. However, I did fix one bug which I spotted: Tag_CPU_arch_profile was not being emitted for v6M. Differential revision: https://reviews.llvm.org/D31812 llvm-svn: 300547
* This patch closes PR#32216: Better testing of schedule model instruction ↵Andrew V. Tischenko2017-04-141-2/+2
| | | | | | | | latencies/throughputs. The details are here: https://reviews.llvm.org/D30941 llvm-svn: 300311
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-053-46/+40
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-031-15/+71
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* Revert "Dont emit Mapping symbols for sections that contain only data."Weiming Zhao2017-03-281-68/+14
| | | | | | | | It breaks some lld tests. This reverts commit 3a50eea6d9732ab40e9a7aebe6be777b53a8b35c. llvm-svn: 298932
* Dont emit Mapping symbols for sections that contain only data.Weiming Zhao2017-03-281-14/+68
| | | | | | | | | | | | | | | | | Summary: Dont emit mapping symbols for sections that contain only data. Patched by Shankar Easwaran <shankare@codeaurora.org> Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 298901
* [ARM] Fix triple format in test branch disassemble testAndre Vieira2017-03-171-4/+26
| | | | | | | | | | | | Fixing triple format in the tests added for the branch label fix for Thumb Targets. Also recommitting previously approved patch, see https://reviews.llvm.org/D30943. Reviewed by: samparker Differential Revision: https://reviews.llvm.org/D30987 llvm-svn: 298056
* Reverting r297821 due to breaking lld test.Sam Parker2017-03-151-55/+33
| | | | llvm-svn: 297838
* [ARM] Fix for branch label disassembly for ThumbSam Parker2017-03-151-33/+55
| | | | | | | | | | | | | | | | | Different MCInstrAnalysis classes for arm and thumb mode, each with their own evaluateBranch implementation. I added a test case and fixed the coff-relocations test to use '<label>:' rather than '<label>' in the CHECK-LABEL entries, since the ones without the colon would match branch targets. Might be worth noticing that llvm-objdump does not lookup the relocation and thus assigns it a target depending on the encoded immediate which #0, so it thinks it branches to the next instruction. Committed on behalf of Andre Vieira (avieira). Differential Revision: https://reviews.llvm.org/D30943 llvm-svn: 297821
* Fix asm printing of associated sections.Evgeniy Stepanov2017-03-141-1/+2
| | | | | | | Make MCSectionELF::AssociatedSection be a link to a symbol, because that's how it works in the assembly, and use it in the asm printer. llvm-svn: 297769
* Fix typo in commentArtyom Skrobov2017-03-141-1/+1
| | | | llvm-svn: 297742
* [ARM] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-081-6/+7
| | | | | | This is preparation to reduce MC headers dependencies. llvm-svn: 294525
* [ARM] Make RWPI use movw/movt when availableChristof Douma2017-02-072-3/+23
| | | | | | | | | | | | | | | | | When constructing global address literals while targeting the RWPI relocation model. LLVM currently only uses literal pools. If MOVW/MOVT instructions are available we can use these instead. Beside being more efficient it allows -arm-execute-only to work with -relocation-model=RWPI as well. When we generate MOVW/MOVT for global addresses when targeting the RWPI relocation model, we need to use base relative relocations. This patch does the needed plumbing in MC to generate these for MOVW/MOVT. Differential Revision: https://reviews.llvm.org/D29487 Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d llvm-svn: 294298
* Change how we handle section symbols on ELF.Rafael Espindola2017-02-021-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ELF every section can have a corresponding section symbol. When in an assembly file we have .quad .text the '.text' refers to that symbol. The way we used to handle them is to leave .text an undefined symbol until the very end when the object writer would map them to the actual section symbol. The problem with that is that anything before the end would see an undefined symbol. This could result in bad diagnostics (test/MC/AArch64/label-arithmetic-diags-elf.s), or incorrect results when using the asm streamer (est/MC/Mips/expansion-jal-sym-pic.s). Fixing this will also allow using the section symbol earlier for setting sh_link of SHF_METADATA sections. This patch includes a few hacks to avoid changing our behaviour when handling conflicts between section symbols and other symbols. I reported pr31850 to track that. llvm-svn: 293936
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-312-21/+21
| | | | | | minor fixes (NFC). llvm-svn: 293578
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-275-63/+126
| | | | | | minor fixes (NFC). llvm-svn: 293348
* [Assembler] Fix crash when assembling .quad for AArch32.Chad Rosier2017-01-181-1/+2
| | | | | | | | | | | A 64-bit relocation does not exist in 32-bit ARMELF. Report an error instead of crashing. PR23870 Patch by Sanne Wouda (sanwou01). Differential Revision: https://reviews.llvm.org/D28851 llvm-svn: 292373
* Recommit: ARM: sort register lists by encoding in push/pop instructions.Tim Northover2016-11-141-1/+8
| | | | | | | | | | | | | | | | | For example we were producing push {r8, r10, r11, r4, r5, r7, lr} This is misleading (r4, r5 and r7 are actually pushed before the rest), and other components (stack folding recently) often forget to deal with the extra complexity coming from the different order, leading to miscompiles. Finally, we warn about our own code in -no-integrated-as mode without this, which is really not a good idea. Fixed usage of std::sort so that we (hopefully) use instantiations that actually exist in GCC 4.8. llvm-svn: 286881
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