| Commit message (Collapse) | Author | Age | Files | Lines |
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Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.
llvm-svn: 150274
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rdar://10838899
llvm-svn: 150222
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llvm-svn: 149961
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and MIPS ELF backends.
Fixes PR11877
llvm-svn: 149180
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llvm-svn: 149102
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Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
llvm-svn: 149093
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relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
llvm-svn: 149057
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accomodate every target I can think of offhand.
llvm-svn: 148833
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violation -- MC cannot depend on CodeGen.
Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.
Fixing this is likely going to require some non-trivial refactoring.
llvm-svn: 148759
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This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.
llvm-svn: 148686
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llvm-svn: 148578
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llvm-svn: 148495
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llvm-svn: 148456
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llvm-svn: 148455
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
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If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
llvm-svn: 148424
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llvm-svn: 148400
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Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.
rdar://10348687.
llvm-svn: 148366
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llvm-svn: 148364
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llvm-svn: 147870
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llvm-svn: 147867
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llvm-svn: 147855
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Fixes PR11214.
llvm-svn: 147180
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llvm-svn: 147132
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llvm-svn: 147121
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llvm-svn: 147119
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llvm-svn: 147117
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llvm-svn: 147115
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avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
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http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
llvm-svn: 146960
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rdar://9932658
llvm-svn: 146921
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
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llvm-svn: 146409
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llvm-svn: 146057
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
llvm-svn: 146054
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llvm-svn: 145895
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rdar://10069056
llvm-svn: 145885
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Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
llvm-svn: 145881
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Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
llvm-svn: 145871
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llvm-svn: 145711
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llvm-svn: 145420
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Replaces r145318 with a more targetted fix for the relocation handling.
llvm-svn: 145346
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We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
llvm-svn: 144852
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llvm-svn: 144842
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and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
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versions of explicit dependencies.
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
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llvm-svn: 143634
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llvm-svn: 143413
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llvm-svn: 142338
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llvm-svn: 141043
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