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path: root/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-2/+3
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+0
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-0/+14
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-3/+3
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-3/+3
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-13/+29
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-6/+7
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-54/+45
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-071-2/+3
| | | | llvm-svn: 134626
* Sink feature IsThumb into MC layer.Evan Cheng2011-07-071-3/+19
| | | | llvm-svn: 134608
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+3
| | | | llvm-svn: 134606
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-071-17/+16
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-071-0/+46
| | | | | | ARM subtarget info available to MC. llvm-svn: 134569
* Add ARM MC registry routines.Evan Cheng2011-07-061-0/+74
llvm-svn: 134547
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