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path: root/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-271-10/+22
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-261-5/+14
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-1/+2
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
| | | | | | | | | The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 llvm-svn: 152268
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Revert r150222, as the clang driver now handles this properly.Jim Grosbach2012-02-101-11/+3
| | | | | | | Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. llvm-svn: 150274
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 llvm-svn: 150222
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-2/+3
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Remove NaClModeDavid Meyer2011-10-181-8/+0
| | | | llvm-svn: 142338
* ARM Darwin default relocation model is PIC.Jim Grosbach2011-09-301-2/+5
| | | | | | | This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-4/+7
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* ARMv7a has the PKH instructions.Jim Grosbach2011-09-141-2/+2
| | | | llvm-svn: 139753
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-2/+3
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+8
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Fix typo in comment.Nick Lewycky2011-09-051-1/+1
| | | | llvm-svn: 139122
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng2011-08-231-5/+8
| | | | | | from MC. llvm-svn: 138367
* The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer2011-08-091-10/+0
| | | | | | instruction so target specific analysis isn't needed anymore. llvm-svn: 137151
* Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer2011-08-081-0/+53
| | | | | | | | | of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. llvm-svn: 137059
* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-261-5/+5
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-5/+5
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-251-0/+13
| | | | llvm-svn: 135974
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-2/+37
| | | | llvm-svn: 135825
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-221-25/+21
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-2/+3
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+0
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-0/+14
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-3/+3
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-3/+3
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-13/+29
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-6/+7
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-54/+45
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-071-2/+3
| | | | llvm-svn: 134626
* Sink feature IsThumb into MC layer.Evan Cheng2011-07-071-3/+19
| | | | llvm-svn: 134608
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+3
| | | | llvm-svn: 134606
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-071-17/+16
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-071-0/+46
| | | | | | ARM subtarget info available to MC. llvm-svn: 134569
* Add ARM MC registry routines.Evan Cheng2011-07-061-0/+74
llvm-svn: 134547
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