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path: root/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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* ARMAsmBackend uses a factory method to generate binary file format specificJoe Abbey2014-09-161-245/+186
| | | | | | | | | | | | | | | | | objects. There were a few FIXMEs in ARMAsmBackend.cpp suggesting the class definitions should be in a separate file. Starting with ARMAsmBackend, the class definition has been put in a header file, and #includes reduced. Each sub-type of ARMAsmBackend is now in its own header file. Derived types have been painted with a different color of bike-shed: s/DarwinARMAsmBackend/ARMAsmBackendDarwin/g s/ARMWinCOFFAsmBackend/ARMAsmBackendWinCOFF/g s/ELFARMAsmBackend/ARMAsmBackendELF/g Finally, clang-format has been run across ARMAsmBackend.cpp llvm-svn: 217866
* Add missing override on ARMAsmBackend's dtor.JF Bastien2014-09-021-2/+1
| | | | | | | | | | Test Plan: ninja check && ninja clang-test Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D5075 llvm-svn: 216912
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-301-4/+4
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-201-1/+4
| | | | llvm-svn: 209200
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-081-0/+4
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-061-37/+46
| | | | llvm-svn: 208076
* MC: support FK_SecRel_4 for Windows on ARMSaleem Abdulrasool2014-05-041-0/+5
| | | | | | | | | Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. llvm-svn: 207941
* Add WoA object file emission supportSaleem Abdulrasool2014-04-271-10/+20
| | | | | | | | | | | | | | | | | | | | | | Introduce support for WoA PE/COFF object file emission from LLVM. Add the new target specific PE/COFF Streamer (ARMWinCOFFStreamer) that handles the ARM specific behaviour of PE/COFF object emission. ARM exception information is not yet emitted and is a TODO item. The ARM specific object writer (ARMWinCOFFObjectWriter) handles the ARM specific relocation handling in conjunction with the WinCOFFObjectWriter in the MC layer. The MC layer needs to be updated to deal with the relocation adjustments. Branch relocations are adjusted by 4 bytes (unlikely their ELF counterparts). Minor tweaks to switch multiple conditional checks into equivalent switch statements. The ObjectFileInfo is updated to relax the object file setup for Windows COFF. Move the architecture checks into an assertion. Windows COFF is currently only supported on x86, x86_64, and ARM (thumb). Rather than defaulting to ELF, we will refuse to generate an object file. This is better though as you do not get an (arbitrary) object file which is different from the request. llvm-svn: 207345
* Spread some const around for non-mutating uses of MCSymbolData.David Blaikie2014-04-241-1/+1
| | | | | | | | I discovered this const-hole while attempting to coalesnce the Symbol and SymbolMap data structures. There's some pending issues with that, but I figured this change was easy to flush early. llvm-svn: 207124
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-011-4/+4
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* ARM: change parameter names of the ELFARMAsmBackend constructorChristian Pirker2014-03-311-2/+2
| | | | | | | I removed the underscore at the beginning of the parameter name, because of a comment from Tim. llvm-svn: 205215
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-291-30/+12
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* Add const.Rafael Espindola2014-03-281-2/+2
| | | | llvm-svn: 205013
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-13/+140
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-13/+14
| | | | | | class. llvm-svn: 203439
* Just returning false is the default.Rafael Espindola2014-02-061-4/+0
| | | | llvm-svn: 200890
* ARM: Resolve thumb_bl fixup in same MCFragment.Logan Chien2014-02-051-1/+8
| | | | | | | | | | | | | | In Thumb1 mode, bl instruction might be selected for branches between basic blocks in the function if the offset is greater than 2KB. However, this might cause SEGV because the destination symbol is not marked as thumb function and the execution mode will be reset to ARM mode. Since we are sure that these symbols are in the same data fragment, we can simply resolve these local symbols, and don't emit any relocation information for this bl instruction. llvm-svn: 200842
* ARM: support tlscall relocationsSaleem Abdulrasool2014-01-301-0/+6
| | | | | | | | | | | | | | This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
* MC: whitespaceSaleem Abdulrasool2014-01-261-57/+56
| | | | | | Fix indentation, remove unnecessary line. NFC. llvm-svn: 200158
* Remove support for armv7f slice. <rdar://problem/12478440>Bob Wilson2014-01-151-1/+0
| | | | | | This was never used for anything so we should just get rid of it. llvm-svn: 199337
* Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions thatKevin Enderby2014-01-101-1/+20
| | | | | | | | | branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 llvm-svn: 198904
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-061-1/+1
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-091-1/+3
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-011-16/+16
| | | | llvm-svn: 189728
* Revert "Fix the build broken by r189315." and "Move everything depending on ↵Charles Davis2013-08-271-16/+16
| | | | | | | | | Object/MachOFormat.h over to Support/MachO.h." This reverts commits r189319 and r189315. r189315 broke some tests on what I believe are big-endian platforms. llvm-svn: 189321
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-08-271-16/+16
| | | | llvm-svn: 189315
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-221-1/+1
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-111-1/+4
| | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). llvm-svn: 183736
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-111-1/+1
| | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? llvm-svn: 183728
* ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
| | | | | | FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk. llvm-svn: 183727
* Whitespace.NAKAMURA Takumi2013-06-111-5/+5
| | | | llvm-svn: 183726
* Follow up of commit r172472.Quentin Colombet2013-01-141-28/+15
| | | | | | Refactor the big if/else sequence into one string switch for ARM subtype selection. llvm-svn: 172475
* Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively ↵Quentin Colombet2013-01-141-0/+9
| | | | | | | | cortex-m0, cortex-m3, and cortex-m4 on the backend side. Adds new subtype values for the MachO format and use them when the related triple are set. llvm-svn: 172472
* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-2/+2
| | | | | | No change in functionality. llvm-svn: 171822
* Correct ARM NOP encodingDavid Sehr2012-12-051-1/+1
| | | | | | | | | | The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html llvm-svn: 169420
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer2012-11-241-63/+46
| | | | | | The implementations already diverged a bit, merge them back together. llvm-svn: 168542
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-011-1/+3
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. llvm-svn: 164974
* Add LLVM support for Swift.Bob Wilson2012-09-291-0/+9
| | | | llvm-svn: 164899
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-181-1/+1
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-31/+57
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach2012-04-121-0/+3
| | | | | | | | They reference the PC directly, so things work properly that way. rdar://11231229 llvm-svn: 154576
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 llvm-svn: 153780
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-301-4/+8
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Prune some includes and forward declarations.Craig Topper2012-03-261-0/+1
| | | | llvm-svn: 153429
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
| | | | | | rdar://11059157 llvm-svn: 153055
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-2/+18
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
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