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path: root/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-091-1/+3
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-011-16/+16
| | | | llvm-svn: 189728
* Revert "Fix the build broken by r189315." and "Move everything depending on ↵Charles Davis2013-08-271-16/+16
| | | | | | | | | Object/MachOFormat.h over to Support/MachO.h." This reverts commits r189319 and r189315. r189315 broke some tests on what I believe are big-endian platforms. llvm-svn: 189321
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-08-271-16/+16
| | | | llvm-svn: 189315
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-221-1/+1
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-111-1/+4
| | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). llvm-svn: 183736
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-111-1/+1
| | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? llvm-svn: 183728
* ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
| | | | | | FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk. llvm-svn: 183727
* Whitespace.NAKAMURA Takumi2013-06-111-5/+5
| | | | llvm-svn: 183726
* Follow up of commit r172472.Quentin Colombet2013-01-141-28/+15
| | | | | | Refactor the big if/else sequence into one string switch for ARM subtype selection. llvm-svn: 172475
* Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively ↵Quentin Colombet2013-01-141-0/+9
| | | | | | | | cortex-m0, cortex-m3, and cortex-m4 on the backend side. Adds new subtype values for the MachO format and use them when the related triple are set. llvm-svn: 172472
* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-2/+2
| | | | | | No change in functionality. llvm-svn: 171822
* Correct ARM NOP encodingDavid Sehr2012-12-051-1/+1
| | | | | | | | | | The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html llvm-svn: 169420
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer2012-11-241-63/+46
| | | | | | The implementations already diverged a bit, merge them back together. llvm-svn: 168542
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-011-1/+3
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. llvm-svn: 164974
* Add LLVM support for Swift.Bob Wilson2012-09-291-0/+9
| | | | llvm-svn: 164899
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-181-1/+1
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-31/+57
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach2012-04-121-0/+3
| | | | | | | | They reference the PC directly, so things work properly that way. rdar://11231229 llvm-svn: 154576
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 llvm-svn: 153780
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-301-4/+8
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Prune some includes and forward declarations.Craig Topper2012-03-261-0/+1
| | | | llvm-svn: 153429
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
| | | | | | rdar://11059157 llvm-svn: 153055
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-2/+18
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* Silence warnings about mixing enums.Benjamin Kramer2012-01-191-3/+2
| | | | llvm-svn: 148495
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
| | | | llvm-svn: 148456
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
| | | | llvm-svn: 148455
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 llvm-svn: 148424
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-181-11/+11
| | | | llvm-svn: 148400
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
| | | | | | | | | | Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. llvm-svn: 148366
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-181-0/+15
| | | | llvm-svn: 148364
* Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola2011-12-221-2/+1
| | | | llvm-svn: 147115
* Reduce the exposure of Triple::OSType in the ELF object writer. This willRafael Espindola2011-12-211-7/+8
| | | | | | | avoid including ADT/Triple.h in many places when the target specific bits are moved. llvm-svn: 147059
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-2/+15
| | | | | | rdar://9932658 llvm-svn: 146921
* Tidy up value checking.Jim Grosbach2011-12-061-1/+2
| | | | llvm-svn: 145895
* Fix ARM handling of tBcc branch relaxation.Jim Grosbach2011-12-061-3/+5
| | | | | | rdar://10069056 llvm-svn: 145885
* Move target-specific logic out of generic MCAssembler.Jim Grosbach2011-12-061-0/+16
| | | | | | | | Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. llvm-svn: 145881
* Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach2011-12-051-3/+24
| | | | | | | Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. llvm-svn: 145871
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
| | | | | | | We don't (yet) have the granularity in the fixups to be specific about which bitranges are affected. That's a future cleanup, but we're not there yet. llvm-svn: 144852
* Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach2011-11-161-1/+1
| | | | llvm-svn: 144842
* ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach2011-11-011-1/+1
| | | | llvm-svn: 143413
* Correct for my over-eager delete finger.Jim Grosbach2011-09-301-0/+1
| | | | llvm-svn: 140892
* ARM Fixup valus for movt/movw are for the whole value.Jim Grosbach2011-09-301-7/+0
| | | | | | | | | Remove an assert that was expecting only the relevant 16bit portion for the fixup being handled. Also kill some dead code in the T2 portion. rdar://9653509 llvm-svn: 140861
* ARM asm backend initialize isThumbMode based on target triple.Jim Grosbach2011-08-241-1/+1
| | | | llvm-svn: 138501
* Thumb assembly parsing and encoding for LDR(literal).Jim Grosbach2011-08-191-1/+1
| | | | llvm-svn: 138052
* ARM Thumb blx instruction fixup has same data range as bl.Jim Grosbach2011-08-181-1/+1
| | | | | | | | | These fixups are handled poorly in general, and should have a single contiguous range of bits per fixup type, but that's not how they're currently organized, so for now in complex ones like for blx, we just tell the emitter it's OK for the fixup to munge any bit it wants. llvm-svn: 137947
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