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llvm-svn: 119059
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
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with movi + orr.
llvm-svn: 118945
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
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llvm-svn: 118141
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
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llvm-svn: 118139
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
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the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
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llvm-svn: 117571
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integer values), not with the addrmode2 encoding.
llvm-svn: 117429
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
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llvm-svn: 117291
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
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llvm-svn: 115845
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"lane" operand modifier.
llvm-svn: 115843
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llvm-svn: 115376
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been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
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