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* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-172-1/+8
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-111-3/+13
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-111-0/+7
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-111-0/+8
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* ARM simplify the postidx_reg operand encoding.Jim Grosbach2011-08-051-2/+1
| | | | | | | The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. llvm-svn: 136969
* ARM use a dedicated printer for postidx_reg operands.Jim Grosbach2011-08-052-0/+10
| | | | llvm-svn: 136968
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-042-0/+11
| | | | | | complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-032-6/+15
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* Rewrite the CMake build to use explicit dependencies between libraries,Chandler Carruth2011-07-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | specified in the same file that the library itself is created. This is more idiomatic for CMake builds, and also allows us to correctly specify dependencies that are missed due to bugs in the GenLibDeps perl script, or change from compiler to compiler. On Linux, this returns CMake to a place where it can relably rebuild several targets of LLVM. I have tried not to change the dependencies from the ones in the current auto-generated file. The only places I've really diverged are in places where I was seeing link failures, and added a dependency. The goal of this patch is not to start changing the dependencies, merely to move them into the correct location, and an explicit form that we can control and change when necessary. This also removes a serialization point in the build because we don't have to scan all the libraries before we begin building various tools. We no longer have a step of the build that regenerates a file inside the source tree. A few other associated cleanups fall out of this. This isn't really finished yet though. After talking to dgregor he urged switching to a single CMake macro to construct libraries with both sources and dependencies in the arguments. Migrating from the two macros to that style will be a follow-up patch. Also, llvm-config is still generated with GenLibDeps.pl, which means it still has slightly buggy dependencies. The internal CMake 'llvm-config-like' macro uses the correct explicitly specified dependencies however. A future patch will switch llvm-config generation (when using CMake) to be based on these deps as well. This may well break Windows. I'm getting a machine set up now to dig into any failures there. If anyone can chime in with problems they see or ideas of how to solve them for Windows, much appreciated. llvm-svn: 136433
* ARM rot_imm printing adjustment.Jim Grosbach2011-07-261-1/+1
| | | | | | | Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. llvm-svn: 136154
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-262-0/+15
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth2011-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-252-3/+3
| | | | llvm-svn: 136006
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-251-14/+6
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-1/+1
| | | | llvm-svn: 135825
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-222-0/+7
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-212-18/+44
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-202-0/+21
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-2/+15
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-181-0/+23
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Flesh out ARM Parser support for shifted-register operands.Jim Grosbach2011-07-131-0/+2
| | | | | | | Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-112-34/+0
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-2/+1
| | | | llvm-svn: 134525
* Don't hardcode the %reg format in the streamer.Rafael Espindola2011-06-022-3/+3
| | | | llvm-svn: 132451
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-2/+3
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-042-5/+50
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-312-8/+50
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-312-50/+8
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-312-8/+50
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-312-57/+10
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-302-10/+57
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-242-0/+7
| | | | llvm-svn: 128236
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-2/+5
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Remove some dead patterns.Jim Grosbach2011-03-142-12/+0
| | | | llvm-svn: 127601
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-052-0/+4
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-1/+8
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-142-20/+14
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-3/+0
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Add support for printing out floating point values from the ARM assemblyBill Wendling2011-01-261-2/+27
| | | | | | | parser. The parser will always give us a binary representation of the floating point number. llvm-svn: 124318
* Revert 124230. It was causing test failures.Bill Wendling2011-01-251-4/+2
| | | | llvm-svn: 124233
* The floating point value is encoded in its binary form as an Imm. Convert itBill Wendling2011-01-251-2/+4
| | | | | | appropriately so that it prints out the decimal representation. llvm-svn: 124230
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-132-0/+12
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-142-33/+37
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-0/+3
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-0/+4
| | | | | | 32-bit wide version by adding the .w suffix. llvm-svn: 120838
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-292-12/+0
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-291-1/+0
| | | | llvm-svn: 120310
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-36/+24
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
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