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* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+12
| | | | llvm-svn: 148762
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-0/+10
| | | | llvm-svn: 148745
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+10
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+10
| | | | llvm-svn: 147025
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-0/+11
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-0/+10
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+9
| | | | llvm-svn: 145504
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+7
| | | | llvm-svn: 145464
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-071-2/+2
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
* Fix the issue that r143552 was trying to address the _right_ way. ↵Owen Anderson2011-11-021-2/+6
| | | | | | One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. llvm-svn: 143557
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+11
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+10
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+9
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* whitespace.Jim Grosbach2011-10-211-1/+1
| | | | llvm-svn: 142657
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+5
| | | | llvm-svn: 142441
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+5
| | | | llvm-svn: 141786
* 80 columns.Jim Grosbach2011-10-121-2/+1
| | | | llvm-svn: 141781
* Tidy up. Formatting.Jim Grosbach2011-10-121-2/+2
| | | | llvm-svn: 141780
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+5
| | | | llvm-svn: 141446
* Support a valid, but not very useful, encoding of CPSIE where none of the ↵Owen Anderson2011-10-051-0/+3
| | | | | | AIF bits are set. llvm-svn: 141190
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-1/+12
| | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-32/+3
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-0/+20
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-231-3/+3
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. llvm-svn: 140420
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-211-12/+0
| | | | | | other test failures I caused. llvm-svn: 140284
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-211-0/+23
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* These do not need to be conditional on the presence of CommentStream, as ↵Owen Anderson2011-09-211-12/+12
| | | | | | they have a fallback path now. llvm-svn: 140267
* In the disassembler C API, be careful not to confuse the comment streamer ↵Owen Anderson2011-09-211-12/+12
| | | | | | that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. llvm-svn: 140217
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+16
| | | | llvm-svn: 140078
* Fix disassembly of Thumb2 LDRSH with a #-0 offset.Owen Anderson2011-09-161-1/+3
| | | | llvm-svn: 139943
* Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson2011-09-151-16/+14
| | | | | | return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. llvm-svn: 139876
* Add support for stored annotations to MCInst, and provide facilities for ↵Owen Anderson2011-09-151-1/+17
| | | | | | MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. llvm-svn: 139820
* Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.Owen Anderson2011-09-131-4/+7
| | | | llvm-svn: 139639
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+12
| | | | llvm-svn: 139381
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-0/+8
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-291-1/+3
| | | | llvm-svn: 138754
* When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.Jim Grosbach2011-08-241-0/+1
| | | | | | rdar://10015134 llvm-svn: 138467
* Clean up Thumb load/store multiple definitions.Jim Grosbach2011-08-231-7/+2
| | | | | | | | There is no non-writeback store multiple instruction in Thumb1, so don't define one. As a result load multiple is the only instantiation of the multiclass, so refactor that away entirely. llvm-svn: 138338
* Thumb parsing and encoding support for NOP.Jim Grosbach2011-08-191-0/+7
| | | | | | The irony is not lost that this is not a completely trivial patchset. llvm-svn: 138143
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-181-2/+2
| | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
* Remove extraneous newline from operand print method. PR10569.Jim Grosbach2011-08-171-3/+3
| | | | llvm-svn: 137900
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-1/+7
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-111-3/+13
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-111-0/+7
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-111-0/+8
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* ARM simplify the postidx_reg operand encoding.Jim Grosbach2011-08-051-2/+1
| | | | | | | The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. llvm-svn: 136969
* ARM use a dedicated printer for postidx_reg operands.Jim Grosbach2011-08-051-0/+9
| | | | llvm-svn: 136968
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-041-0/+9
| | | | | | complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-3/+11
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM rot_imm printing adjustment.Jim Grosbach2011-07-261-1/+1
| | | | | | | Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. llvm-svn: 136154
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