| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 1 | -0/+10 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 | 1 | -0/+9 |
| * | whitespace. | Jim Grosbach | 2011-10-21 | 1 | -1/+1 |
| * | ARM VTBL (one register) assembly parsing and encoding. | Jim Grosbach | 2011-10-18 | 1 | -0/+5 |
| * | ARM parsing and encoding for the <option> form of LDC/STC instructions. | Jim Grosbach | 2011-10-12 | 1 | -0/+5 |
| * | 80 columns. | Jim Grosbach | 2011-10-12 | 1 | -2/+1 |
| * | Tidy up. Formatting. | Jim Grosbach | 2011-10-12 | 1 | -2/+2 |
| * | ARM NEON assembly parsing and encoding for VDUP(scalar). | Jim Grosbach | 2011-10-07 | 1 | -0/+5 |
| * | Support a valid, but not very useful, encoding of CPSIE where none of the AIF... | Owen Anderson | 2011-10-05 | 1 | -0/+3 |
| * | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby | 2011-10-04 | 1 | -1/+12 |
| * | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach | 2011-09-30 | 1 | -32/+3 |
| * | Check in a patch that has already been code reviewed by Owen that I'd forgott... | James Molloy | 2011-09-28 | 1 | -0/+20 |
| * | Post-index loads/stores in still need to print the post-indexed immediate, ev... | Owen Anderson | 2011-09-23 | 1 | -3/+3 |
| * | Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix o... | Owen Anderson | 2011-09-21 | 1 | -12/+0 |
| * | Print out immediate offset versions of PC-relative load/store instructions as... | Owen Anderson | 2011-09-21 | 1 | -0/+23 |
| * | These do not need to be conditional on the presence of CommentStream, as they... | Owen Anderson | 2011-09-21 | 1 | -12/+12 |
| * | In the disassembler C API, be careful not to confuse the comment streamer tha... | Owen Anderson | 2011-09-21 | 1 | -12/+12 |
| * | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach | 2011-09-19 | 1 | -0/+16 |
| * | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson | 2011-09-16 | 1 | -1/+3 |
| * | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson | 2011-09-15 | 1 | -16/+14 |
| * | Add support for stored annotations to MCInst, and provide facilities for MC-b... | Owen Anderson | 2011-09-15 | 1 | -1/+17 |
| * | Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. | Owen Anderson | 2011-09-13 | 1 | -4/+7 |
| * | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach | 2011-09-09 | 1 | -0/+12 |
| * | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy | 2011-09-07 | 1 | -0/+8 |
| * | Improve handling of #-0 offsets for many more pre-indexed addressing modes. | Owen Anderson | 2011-08-29 | 1 | -1/+3 |
| * | When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. | Jim Grosbach | 2011-08-24 | 1 | -0/+1 |
| * | Clean up Thumb load/store multiple definitions. | Jim Grosbach | 2011-08-23 | 1 | -7/+2 |
| * | Thumb parsing and encoding support for NOP. | Jim Grosbach | 2011-08-19 | 1 | -0/+7 |
| * | Thumb assembly parsing and encoding for LDM instruction. | Jim Grosbach | 2011-08-18 | 1 | -2/+2 |
| * | Remove extraneous newline from operand print method. PR10569. | Jim Grosbach | 2011-08-17 | 1 | -3/+3 |
| * | ARM clean up the imm_sr operand class representation. | Jim Grosbach | 2011-08-17 | 1 | -1/+7 |
| * | Correct immediate range for shifter operands. Patch by James Molloy, with ad... | Owen Anderson | 2011-08-11 | 1 | -3/+13 |
| * | ARM push of a single register encodes as pre-indexed STR. | Jim Grosbach | 2011-08-11 | 1 | -0/+7 |
| * | ARM pop of a single register encodes as post-indexed LDR. | Jim Grosbach | 2011-08-11 | 1 | -0/+8 |
| * | ARM simplify the postidx_reg operand encoding. | Jim Grosbach | 2011-08-05 | 1 | -2/+1 |
| * | ARM use a dedicated printer for postidx_reg operands. | Jim Grosbach | 2011-08-05 | 1 | -0/+9 |
| * | LDCL_POST and STCL_POST need one's-complement offsets, rather than two's comp... | Owen Anderson | 2011-08-04 | 1 | -0/+9 |
| * | ARM refactoring assembly parsing of memory address operands. | Jim Grosbach | 2011-08-03 | 1 | -3/+11 |
| * | ARM rot_imm printing adjustment. | Jim Grosbach | 2011-07-26 | 1 | -1/+1 |
| * | ARM cleanup of rot_imm encoding. | Jim Grosbach | 2011-07-26 | 1 | -0/+14 |
| * | ARM assembly parsing and encoding for SSAT16 instruction. | Jim Grosbach | 2011-07-25 | 1 | -2/+2 |
| * | ARM assembly parsing and encoding for SSAT instruction. | Jim Grosbach | 2011-07-25 | 1 | -14/+6 |
| * | Sink ARM mc routines into MCTargetDesc. | Evan Cheng | 2011-07-23 | 1 | -1/+1 |
| * | ARM SSAT instruction 5-bit immediate handling. | Jim Grosbach | 2011-07-22 | 1 | -0/+6 |
| * | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson | 2011-07-21 | 1 | -17/+42 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | ARM PKH shift ammount operand printing tweaks. | Jim Grosbach | 2011-07-20 | 1 | -0/+19 |
| * | Tweak ARM assembly parsing and printing of MSR instruction. | Jim Grosbach | 2011-07-19 | 1 | -2/+15 |
| * | Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple... | Owen Anderson | 2011-07-18 | 1 | -0/+23 |
| * | Flesh out ARM Parser support for shifted-register operands. | Jim Grosbach | 2011-07-13 | 1 | -0/+2 |
