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* Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instructionJim Grosbach2010-07-162-14/+16
| | | | | | | and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. llvm-svn: 108570
* Convert some tab stops into spaces.Duncan Sands2010-07-121-2/+2
| | | | llvm-svn: 108130
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-261-2/+0
| | | | llvm-svn: 106927
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-251-6/+6
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
* Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson2010-06-251-16/+3
| | | | | | Renumber MiscFrm to 25. llvm-svn: 106916
* Silence compiler warnings.Dan Gohman2010-06-191-3/+3
| | | | llvm-svn: 106360
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-182-41/+43
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-32/+2
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-4/+4
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-4/+4
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-4/+4
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Modified some assert() msg strings; no other functionality change.Johnny Chen2010-04-211-14/+14
| | | | llvm-svn: 102008
* Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen2010-04-213-14/+68
| | | | | | | | before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
* Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),Johnny Chen2010-04-201-6/+14
| | | | | | instead of just asserting. llvm-svn: 101942
* For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen2010-04-201-5/+5
| | | | | | | | | Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
* Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands whereJohnny Chen2010-04-201-1/+4
| | | | | | d==15 is considered illegal. Return false instead of assert(). llvm-svn: 101852
* More IT instruction error-handling improvements from fuzzing.Johnny Chen2010-04-201-3/+17
| | | | llvm-svn: 101839
* Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen2010-04-193-5/+11
| | | | llvm-svn: 101827
* According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen2010-04-191-8/+13
| | | | | | | | | | Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. llvm-svn: 101817
* Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operandJohnny Chen2010-04-191-3/+6
| | | | | | | | instructions should have Rd (Inst{11-8}) != 0b1111. Ref: A6.3 32-bit Thumb instruction encoding A6.3.11 Data-processing (shifted register) llvm-svn: 101788
* ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen2010-04-191-10/+22
| | | | | | VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. llvm-svn: 101784
* Cast to (uint64_t) instead of relying on the "ul" suffix.Johnny Chen2010-04-161-1/+1
| | | | llvm-svn: 101573
* Fixed logic error. Should check Builder for validity before calling SetSessionJohnny Chen2010-04-161-3/+2
| | | | | | on it. llvm-svn: 101563
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-161-1/+2
| | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). llvm-svn: 101557
* DEBUG() print out "Unknown format" msg.Johnny Chen2010-04-151-1/+3
| | | | llvm-svn: 101382
* Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.Johnny Chen2010-04-152-4/+7
| | | | llvm-svn: 101329
* Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()Johnny Chen2010-04-141-0/+6
| | | | | | | function checks whether we have a valid submode for VLDM/VSTM (must be either "ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char). llvm-svn: 101306
* For t2BFI disassembly, apply the same error checking as in r101205.Johnny Chen2010-04-142-3/+6
| | | | | | Change the error msg to read "Encoding error: msb < lsb". llvm-svn: 101293
* Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()Johnny Chen2010-04-144-319/+352
| | | | | | | | | | | | | | was asserting because the (RegClass, RegNum) combination doesn't make sense from an encoding point of view. Since getRegisterEnum() is used all over the place, to change the code to check for encoding error after each call would not only bloat the code, but also make it less readable. An Err flag is added to the ARMBasicMCBuilder where a client can set a non-zero value to indicate some kind of error condition while building up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false if a non-zero value is detected. llvm-svn: 101290
* Fixed another assert exposed by fuzzing. Now, when an encoding error occursJohnny Chen2010-04-141-4/+14
| | | | | | | involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler just returns false, instead of assert, to indicate disassembly error. llvm-svn: 101205
* Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalidJohnny Chen2010-04-142-10/+15
| | | | | | | instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder instance and the client just returns false to indicate disassembly error. llvm-svn: 101201
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-132-2/+19
| | | | | | | | | | | | | | | code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. llvm-svn: 101179
* Missed this one line for the previous checkin to fix build warnings.Johnny Chen2010-04-071-1/+0
| | | | llvm-svn: 100697
* Fixed warnings pointed out by clang.Johnny Chen2010-04-071-7/+19
| | | | llvm-svn: 100696
* Fixed warnings pointed out by clang.Johnny Chen2010-04-071-2/+16
| | | | | | Next to work on is ARMDisassemblerCore.cpp. llvm-svn: 100695
* Fixed 3 warnings pointed out by clang.Johnny Chen2010-04-071-3/+3
| | | | llvm-svn: 100693
* Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call inJohnny Chen2010-04-071-0/+16
| | | | | | ARMDecoderEmitter.cpp, with FIXME comment. llvm-svn: 100690
* Get rid of traling whitespaces. No functionality change.Johnny Chen2010-04-051-1/+1
| | | | llvm-svn: 100404
* The disassembler impl. of MCDisassembler::getInstruction() was using the patternJohnny Chen2010-04-051-5/+23
| | | | | | | | | | | | | uint32_t insn; MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL) to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the interpretation of byte order up to the host machine and causes PPC test cases of arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for reading the memory contents and shift the bytes into place for the 32-bit uint variable in the ARM case and 16-bit halfword in the Thumb case. llvm-svn: 100403
* Temporarily remove to disable building of ARM disassembler.Evan Cheng2010-04-051-16/+0
| | | | llvm-svn: 100380
* Re-apply 100265 but instead disable building of ARM disassembly for now.Evan Cheng2010-04-052-86/+29
| | | | llvm-svn: 100379
* Reverting 100265 to try to get buildbots green again. Lots of self-hosting ↵Evan Cheng2010-04-052-29/+86
| | | | | | buildbots started complaining since this commit. Also xfail ARM disassembly tests. llvm-svn: 100378
* Get rid of the middleman (ARMAlgorithm), which causes more trouble than theJohnny Chen2010-04-032-86/+29
| | | | | | | abstraction it brings. And also get rid of the atexit() handler, it does not belong in the lib directory. :-) llvm-svn: 100265
* Fix comment.Johnny Chen2010-04-031-2/+2
| | | | llvm-svn: 100259
* Register ARMAlgorithm::DoCleanup() to be called on exit to free the memoryJohnny Chen2010-04-032-1/+13
| | | | | | occuplied by the cached ARMAlgorithm objects. llvm-svn: 100258
* Fix another build warning.Johnny Chen2010-04-021-0/+2
| | | | llvm-svn: 100251
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-026-0/+6369
| | | | | | | | | | backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-166-6411/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-166-0/+6411
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
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