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* Avoid -Wunused-variable in -asserts buildsMatt Beaumont-Gay2011-03-221-6/+4
| | | | llvm-svn: 128048
* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-191-3/+4
| | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-181-10/+2
| | | | | | Remove the offending logic and update the test cases. llvm-svn: 127843
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-171-16/+13
| | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. llvm-svn: 127833
* There were two issues fixed:Johnny Chen2011-03-151-12/+5
| | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-6/+9
| | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-091-0/+3
| | | | | | | | | The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354
* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-2/+4
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
* Add missing whitespace in the formatting.Kevin Enderby2011-02-281-1/+1
| | | | llvm-svn: 126687
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-1/+13
| | | | | | needed two predicate operands before the imm operand. llvm-svn: 126662
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-182-10/+16
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-142-25/+44
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-082-10/+45
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* PR9030: Fix disassembly of ARM "mov pc, lr" instruction.Bob Wilson2011-01-281-2/+2
| | | | | | Patch by Jyun-Yan You. llvm-svn: 124492
* CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some ↵NAKAMURA Takumi2010-12-291-2/+2
| | | | | | files in Target/ARM and Target/X86. llvm-svn: 122623
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-072-40/+5
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-3/+0
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-302-40/+4
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* s/ARM::BRIND/ARM::BX/g to coincide with r120366.Bill Wendling2010-11-301-3/+3
| | | | llvm-svn: 120371
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-292-75/+2
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-162-57/+46
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-032-9/+9
| | | | llvm-svn: 118152
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-7/+2
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-9/+12
| | | | llvm-svn: 117571
* Detabify and clean up 80 column violations.Jim Grosbach2010-10-133-40/+50
| | | | llvm-svn: 116454
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-2/+6
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.Francois Pichet2010-10-111-1/+7
| | | | llvm-svn: 116201
* Add ARM Disassembler to the CMake build.Oscar Fuentes2010-09-282-2/+10
| | | | llvm-svn: 114949
* Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer2010-09-171-2/+2
| | | | llvm-svn: 114240
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-161-1/+4
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach2010-09-151-8/+7
| | | | | | | moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. llvm-svn: 114021
* Reapply r113875 with additional cleanups.Jim Grosbach2010-09-141-35/+5
| | | | | | | | | | | | | | | "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. llvm-svn: 113903
* ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to ↵NAKAMURA Takumi2010-09-081-2/+2
| | | | | | Cygwin-1.5, following up to r113255. llvm-svn: 113345
* hopefully fix a problem building on cygwin-1.5Chris Lattner2010-09-071-2/+2
| | | | llvm-svn: 113255
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-8/+7
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* explicitly handle no-op cases for clarity. Fixes clang warning.Jim Grosbach2010-08-171-0/+3
| | | | llvm-svn: 111260
* Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson2010-08-172-15/+22
| | | | | | | printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
* Move the Thumb2 SSAT and USAT optional shift operator out of theBob Wilson2010-08-131-9/+13
| | | | | | instruction opcode. This fixes part of PR7792. llvm-svn: 111047
* Refactor the code for disassembling Thumb2 saturate instructions along theBob Wilson2010-08-131-56/+39
| | | | | | same lines as the change I made for ARM saturate instructions. llvm-svn: 111029
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-2/+9
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen2010-08-122-0/+9
| | | | | | | | | | entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
* Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen2010-08-112-5/+2
| | | | | | Added two test cases to arm-tests.txt. llvm-svn: 110880
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-112-8/+11
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-111-1/+1
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-112-86/+63
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Add support for disassembling VMVN (immediate) instructions. PR7747.Bob Wilson2010-07-311-0/+4
| | | | llvm-svn: 109946
* Add a check in the ARM disassembler for NEON instructions that wouldBob Wilson2010-07-301-5/+9
| | | | | | | reference registers past the end of the NEON register file, and report them as invalid instead of asserting when trying to print them. PR7746. llvm-svn: 109933
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-302-40/+54
| | | | | | | | | | | | | | | | | | | | | | | | have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 llvm-svn: 109842
* Don't assert on an unrecognized BrMiscFrm instruction.Bob Wilson2010-07-291-1/+0
| | | | | | PR7745. llvm-svn: 109788
* prune #includes a little.Chris Lattner2010-07-201-1/+2
| | | | llvm-svn: 108929
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