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* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+5
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
| | | | | | And two test cases. llvm-svn: 129090
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* A8.6.393Johnny Chen2011-04-061-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-1/+1
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-1/+7
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* A7.3 register encodingJohnny Chen2011-04-051-0/+10
| | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-7/+19
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+10
| | | | llvm-svn: 128913
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-051-5/+2
| | | | | | Finish what r128736 started. llvm-svn: 128903
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-2/+49
| | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-042-5/+19
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-7/+132
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-041-2/+5
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-5/+13
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-011-0/+8
| | | | | | | | should reject the instruction as invalid. llvm-svn: 128734
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-3/+4
| | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-3/+9
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-311-2/+13
| | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-9/+3
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-3/+9
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-12/+12
| | | | | | actually exist. llvm-svn: 128461
* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-282-5/+18
| | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-262-10/+39
| | | | llvm-svn: 128322
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-2/+3
| | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
* Modify DisassembleThumb2LdStEx() to be more robust/correct in light of ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+5
| | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285
* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-4/+11
| | | | | | rdar://problem/9186136 llvm-svn: 128283
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-9/+9
| | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-2/+7
| | | | llvm-svn: 128243
* Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!Johnny Chen2011-03-241-3/+1
| | | | llvm-svn: 128241
* T2 Load/Store Multiple:Johnny Chen2011-03-241-1/+1
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-241-3/+2
| | | | llvm-svn: 128238
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+16
| | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. llvm-svn: 128226
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-241-0/+2
| | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. llvm-svn: 128220
* CPS3p: Let's reject impossible imod values by returning false from the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DisassembleMiscFrm() function. Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing) Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- Before: cpsUnknown imod operand UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123! After: /Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding 0x93 0x1c 0x2 0xf1 ^ llvm-svn: 128192
* Load/Store Multiple:Johnny Chen2011-03-241-4/+4
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-2/+7
| | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
* For ARM Disassembler, start a newline to dump the opcode and friends for an ↵Johnny Chen2011-03-221-1/+1
| | | | | | | | instruction. Change inspired by llvm-bug 9530 submitted by Jyun-Yan You. llvm-svn: 128122
* A8.6.399 VSTM:Johnny Chen2011-03-221-12/+2
| | | | | | | | | | | VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103
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