summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Disassembler
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-272-2/+2
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-262-9/+2
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth2011-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-252-20/+8
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-222-4/+0
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Thumb assembly support for SETEND instruction.Jim Grosbach2011-07-221-2/+7
| | | | llvm-svn: 135778
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-212-4/+71
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-2/+4
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-202-12/+8
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-202-2/+10
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-181-2/+2
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-181-7/+7
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-161-7/+7
| | | | llvm-svn: 135343
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-151-7/+7
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135319
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-5/+0
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-3/+4
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-141-1/+1
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+1
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-282-122/+122
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Restore an accidentally removed comment.Cameron Zwarich2011-05-251-0/+1
| | | | llvm-svn: 132044
* Change the order of tBX's operands so that the predicate operands come after theCameron Zwarich2011-05-251-1/+10
| | | | | | | | | target register, matching BX. I filed this bug because I was confused at first: PR10007 - ARM branch instructions have inconsistent predicate operand placement <http://llvm.org/bugs/show_bug.cgi?id=10007> llvm-svn: 132041
* Rename tBX_Rm to tBX.Cameron Zwarich2011-05-251-2/+2
| | | | llvm-svn: 132040
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-3/+4
| | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-1/+1
| | | | | | immediate operand. llvm-svn: 131565
* Fix a bug in the case that there is no add or subtract symbol and the offsetKevin Enderby2011-04-271-2/+6
| | | | | | value is zero so it does not add a NULL expr operand. llvm-svn: 130330
* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
| | | | llvm-svn: 129837
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-1/+1
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-151-0/+27
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-141-4/+41
| | | | | | operations. llvm-svn: 129531
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-6/+14
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-2/+6
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-0/+2
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-122-0/+29
| | | | | | Ld/St Multiple. llvm-svn: 129365
* A8.6.16 BJohnny Chen2011-04-121-0/+5
| | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-2/+5
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-6/+17
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
| | | | llvm-svn: 129288
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-111-0/+68
| | | | | | | | them as invalid instructions. llvm-svn: 129286
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | llvm-svn: 129160
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | llvm-svn: 129148
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
OpenPOWER on IntegriCloud