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* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-202-12/+8
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-202-2/+10
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-181-2/+2
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-181-7/+7
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-161-7/+7
| | | | llvm-svn: 135343
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-151-7/+7
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135319
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-5/+0
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-151-1/+1
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-3/+4
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-141-1/+1
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+1
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-282-122/+122
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Restore an accidentally removed comment.Cameron Zwarich2011-05-251-0/+1
| | | | llvm-svn: 132044
* Change the order of tBX's operands so that the predicate operands come after theCameron Zwarich2011-05-251-1/+10
| | | | | | | | | target register, matching BX. I filed this bug because I was confused at first: PR10007 - ARM branch instructions have inconsistent predicate operand placement <http://llvm.org/bugs/show_bug.cgi?id=10007> llvm-svn: 132041
* Rename tBX_Rm to tBX.Cameron Zwarich2011-05-251-2/+2
| | | | llvm-svn: 132040
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-3/+4
| | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-1/+1
| | | | | | immediate operand. llvm-svn: 131565
* Fix a bug in the case that there is no add or subtract symbol and the offsetKevin Enderby2011-04-271-2/+6
| | | | | | value is zero so it does not add a NULL expr operand. llvm-svn: 130330
* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
| | | | llvm-svn: 129837
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-1/+1
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-151-0/+27
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-141-4/+41
| | | | | | operations. llvm-svn: 129531
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-6/+14
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-2/+6
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-0/+2
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-122-0/+29
| | | | | | Ld/St Multiple. llvm-svn: 129365
* A8.6.16 BJohnny Chen2011-04-121-0/+5
| | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-2/+5
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-6/+17
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
| | | | llvm-svn: 129288
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-111-0/+68
| | | | | | | | them as invalid instructions. llvm-svn: 129286
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | llvm-svn: 129160
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | llvm-svn: 129148
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+5
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
| | | | | | And two test cases. llvm-svn: 129090
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
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