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* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-032-9/+9
| | | | llvm-svn: 118152
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-7/+2
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-9/+12
| | | | llvm-svn: 117571
* Detabify and clean up 80 column violations.Jim Grosbach2010-10-133-40/+50
| | | | llvm-svn: 116454
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-2/+6
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.Francois Pichet2010-10-111-1/+7
| | | | llvm-svn: 116201
* Add ARM Disassembler to the CMake build.Oscar Fuentes2010-09-282-2/+10
| | | | llvm-svn: 114949
* Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer2010-09-171-2/+2
| | | | llvm-svn: 114240
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-161-1/+4
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach2010-09-151-8/+7
| | | | | | | moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. llvm-svn: 114021
* Reapply r113875 with additional cleanups.Jim Grosbach2010-09-141-35/+5
| | | | | | | | | | | | | | | "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. llvm-svn: 113903
* ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to ↵NAKAMURA Takumi2010-09-081-2/+2
| | | | | | Cygwin-1.5, following up to r113255. llvm-svn: 113345
* hopefully fix a problem building on cygwin-1.5Chris Lattner2010-09-071-2/+2
| | | | llvm-svn: 113255
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-8/+7
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* explicitly handle no-op cases for clarity. Fixes clang warning.Jim Grosbach2010-08-171-0/+3
| | | | llvm-svn: 111260
* Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson2010-08-172-15/+22
| | | | | | | printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
* Move the Thumb2 SSAT and USAT optional shift operator out of theBob Wilson2010-08-131-9/+13
| | | | | | instruction opcode. This fixes part of PR7792. llvm-svn: 111047
* Refactor the code for disassembling Thumb2 saturate instructions along theBob Wilson2010-08-131-56/+39
| | | | | | same lines as the change I made for ARM saturate instructions. llvm-svn: 111029
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-2/+9
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen2010-08-122-0/+9
| | | | | | | | | | entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
* Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen2010-08-112-5/+2
| | | | | | Added two test cases to arm-tests.txt. llvm-svn: 110880
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-112-8/+11
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-111-1/+1
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-112-86/+63
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Add support for disassembling VMVN (immediate) instructions. PR7747.Bob Wilson2010-07-311-0/+4
| | | | llvm-svn: 109946
* Add a check in the ARM disassembler for NEON instructions that wouldBob Wilson2010-07-301-5/+9
| | | | | | | reference registers past the end of the NEON register file, and report them as invalid instead of asserting when trying to print them. PR7746. llvm-svn: 109933
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-302-40/+54
| | | | | | | | | | | | | | | | | | | | | | | | have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 llvm-svn: 109842
* Don't assert on an unrecognized BrMiscFrm instruction.Bob Wilson2010-07-291-1/+0
| | | | | | PR7745. llvm-svn: 109788
* prune #includes a little.Chris Lattner2010-07-201-1/+2
| | | | llvm-svn: 108929
* Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instructionJim Grosbach2010-07-162-14/+16
| | | | | | | and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. llvm-svn: 108570
* Convert some tab stops into spaces.Duncan Sands2010-07-121-2/+2
| | | | llvm-svn: 108130
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-261-2/+0
| | | | llvm-svn: 106927
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-251-6/+6
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
* Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson2010-06-251-16/+3
| | | | | | Renumber MiscFrm to 25. llvm-svn: 106916
* Silence compiler warnings.Dan Gohman2010-06-191-3/+3
| | | | llvm-svn: 106360
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-182-41/+43
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-32/+2
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-4/+4
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-4/+4
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-4/+4
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Modified some assert() msg strings; no other functionality change.Johnny Chen2010-04-211-14/+14
| | | | llvm-svn: 102008
* Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen2010-04-213-14/+68
| | | | | | | | before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
* Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),Johnny Chen2010-04-201-6/+14
| | | | | | instead of just asserting. llvm-svn: 101942
* For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen2010-04-201-5/+5
| | | | | | | | | Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
* Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands whereJohnny Chen2010-04-201-1/+4
| | | | | | d==15 is considered illegal. Return false instead of assert(). llvm-svn: 101852
* More IT instruction error-handling improvements from fuzzing.Johnny Chen2010-04-201-3/+17
| | | | llvm-svn: 101839
* Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen2010-04-193-5/+11
| | | | llvm-svn: 101827
* According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen2010-04-191-8/+13
| | | | | | | | | | Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. llvm-svn: 101817
* Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operandJohnny Chen2010-04-191-3/+6
| | | | | | | | instructions should have Rd (Inst{11-8}) != 0b1111. Ref: A6.3 32-bit Thumb instruction encoding A6.3.11 Data-processing (shifted register) llvm-svn: 101788
* ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen2010-04-191-10/+22
| | | | | | VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. llvm-svn: 101784
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