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* ARMDisassembler: loop over ARM decode tablesSjoerd Meijer2017-03-131-57/+20
| | | | | | | | | Loop over the ARM decode tables; this is a clean-up to reduce some code duplication. Differential Revision: https://reviews.llvm.org/D30814 llvm-svn: 297608
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-271-33/+29
| | | | | | minor fixes (NFC). llvm-svn: 293348
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-4/+4
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-3/+3
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-171-8/+26
| | | | | | | | | | | | | | | | | | | Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
* Reverting r272778 because there's an assertionRanjeet Singh2016-06-151-26/+8
| | | | | | failure when running the test CodeGen/ARM/intrinsics-coprocessor.ll llvm-svn: 272791
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-151-8/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D21178 llvm-svn: 272778
* [ARM] Reverting r272544 because clang patch needsRanjeet Singh2016-06-131-26/+8
| | | | | | | to go in as soon as llvm patch has gone in because tests will start breaking in Clang. llvm-svn: 272546
* [ARM] Add mrrc/mrrc2 co-processor intrinsicsRanjeet Singh2016-06-131-8/+26
| | | | | | | | | | | | | MRRC/MRRC2 instruction writes to two registers. The intrinsic definition returns a single uint64_t to represent the write, this is a compact way of representing a write to two 32 bit registers, the alternative might have been two return a struct of 2 uint32_t's but this isn't as nice. Differential Revision: llvm-svn: 272544
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-031-0/+31
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-261-1/+1
| | | | | | No functional change, just moving code around. llvm-svn: 258818
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-251-0/+18
| | | | | | | | This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258682
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-251-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* # This is a combination of 2 commits.Reid Kleckner2016-01-151-18/+0
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-151-0/+18
| | | | llvm-svn: 257884
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-161-23/+0
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-161-8/+66
| | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. Differential Revision: http://reviews.llvm.org/D15039 llvm-svn: 255764
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-161-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* Test commitVinicius Tinti2015-11-201-4/+4
| | | | llvm-svn: 253737
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-281-2/+7
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-241-1/+1
| | | | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248519
* Explicitly clear the MI operand list when getInstruction() is called. Call ↵Cameron Esfahani2015-08-111-20/+0
| | | | | | | | | | | | | | MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler. Summary: Explicitly clear the MI operand list when getInstruction() is called. Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11665 llvm-svn: 244557
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-2/+2
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-2/+2
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-35/+43
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-151/+151
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-43/+35
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-35/+43
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* [ARM] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-161-0/+52
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-2/+2
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-39/+32
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-32/+39
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-39/+32
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-32/+39
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined ↵Bradley Smith2015-01-191-1/+1
| | | | | | encoding rather than unpredictable llvm-svn: 226469
* Remove unused function.Asiri Rathnayake2014-12-021-11/+0
| | | | | | | | | Removing an unused function which is causing one of the build bots to fail. This was introduced in the commit r223113. A proper cleanup of the so_imm tblgen defintion (made redundant by the mod_imm definition) needs to happen soon. llvm-svn: 223115
* Add post-decode checking of HVC instruction.Charlie Turner2014-12-011-1/+23
| | | | | | | | | | | | Add checkDecodedInstruction for post-decode checking of instructions, to catch the corner cases like HVC that don't fit into the general pattern. Needed to check for an invalid condition field in instruction encoding despite HVC not taking a predicate. Patch by Matthew Wahab. Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795 llvm-svn: 222992
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-12/+7
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-101-130/+120
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [ARM] Remove dead code identified by the Clang static analyzer.Tilmann Scheller2014-11-051-2/+0
| | | | llvm-svn: 221358
* [ARM] Honor FeatureD16 in the assembler and disassemblerOliver Stannard2014-11-051-1/+5
| | | | | | | | | | | | | | | Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
* [Thumb2] Improve disassembly of memory hintsOliver Stannard2014-10-231-7/+57
| | | | | | | | | Currently, the ARM disassembler will disassemble the Thumb2 memory hint instructions (PLD, PLDW and PLI), even for targets which do not have these instructions. This patch adds the required checks to the disassmebler. llvm-svn: 220472
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-011-12/+21
| | | | | | | | | | | | This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. llvm-svn: 216874
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-151-0/+25
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* Allow only disassembling of M-class MSR masks that the assembler knows how ↵James Molloy2014-08-011-1/+47
| | | | | | | | | | to assemble back. Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-8/+12
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-011-4/+4
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-2/+6
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-10/+6
| | | | | | class. llvm-svn: 203439
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