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* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* ARM: consolidate MachO checks for ARM asm parserSaleem Abdulrasool2014-04-051-84/+28
| | | | | | | | | | | | | | | | | | | This consolidates the duplicated MachO checks in the directive parsing for various directives that are unsupported for Mach-O. The error message change is unimportant as this restores the behaviour to that prior to the addition of the new directive handling. Furthermore, use a more direct check for MachO targeting rather than an indirect feature check of the assembler. Also simplify the test execution command to avoid temporary files. Further more, perform the check in both object and assembly emission. Whether all non-applicable directives are handled is another question. .fnstart is marked as being unsupported, however, the complementary .fnend is not. The additional unwinding directives are also still honoured. This change does not change that, though, it would be good to validate and mark them as being unsupported if they are unsupported for the MachO emission. llvm-svn: 205678
* Fix for PR18921 (LDRD/STRD part)::Stepan Dyatkovskiy2014-04-041-11/+14
| | | | | | | | Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now. Added new tests. llvm-svn: 205622
* PR19320:Stepan Dyatkovskiy2014-04-031-4/+9
| | | | | | | The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-011-4/+4
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-291-1/+1
| | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 205094
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-2/+4
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* ARM: raise error message when complex SO expressions can't really beJiangning Liu2014-03-271-1/+1
| | | | | | solved as a constant at compilation time. llvm-svn: 204898
* Fix a problem with the ARM assembler incorrectly matching aKevin Enderby2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector list parameter that is using all lanes "{d0[], d2[]}" but can match and instruction with a ”{d0, d2}" parameter. I’m finishing up a fix for proper checking of the unsupported alignments on vld/vst instructions and ran into this. Thus I don’t have a test case at this time. And adding all code that will demonstrate the bug would obscure the very simple one line fix. So if you would indulge me on not having a test case at this time I’ll instead offer up a detailed explanation of what is going on in this commit message. This instruction: vld2.8 {d0[], d2[]}, [r4:64] is not legal as the alignment can only be 16 when the size is 8. Per this documentation: A8.8.325 VLD2 (single 2-element structure to all lanes) <align> The alignment. It can be one of: 16 2-byte alignment, available only if <size> is 8, encoded as a = 1. 32 4-byte alignment, available only if <size> is 16, encoded as a = 1. 64 8-byte alignment, available only if <size> is 32, encoded as a = 1. omitted Standard alignment, see Unaligned data access on page A3-108. So when code is added to the llvm integrated assembler to not match that instruction because of the alignment it then goes on to try to match other instructions and comes across this: vld2.8 {d0, d2}, [r4:64] and and matches it. This is because of the method ARMOperand::isVecListDPairSpaced() is missing the check of the Kind. In this case the Kind is k_VectorListAllLanes . While the name of the method may suggest that this is OK it really should check that the Kind is k_VectorList. As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was used to match {d0[], d2[]} and correctly checks the Kind: bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } where the original ARMOperand::isVecListDPairSpaced() does not check the Kind: bool isVecListDPairSpaced() const { if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } Jim Grosbach has reviewed the change and said: Yep, that sounds right. … And by "right" I mean, "wow, that's a nasty latent bug I'm really, really glad to see fixed." :) rdar://16436683 llvm-svn: 204861
* Fix the ARM VST4 (single 4-element structure from one lane)Kevin Enderby2014-03-261-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! was being printed as: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! rdar://16435096 llvm-svn: 204847
* Fix crashes when assembler directives are used that are notKevin Enderby2014-03-251-1/+64
| | | | | | | | for Mach-O object files by generating an error instead. rdar://16335232 llvm-svn: 204687
* Prune includes in ARM target.Craig Topper2014-03-221-2/+0
| | | | llvm-svn: 204548
* ARM IAS: properly handle function entries in .thumbSaleem Abdulrasool2014-03-221-0/+30
| | | | | | | | | | | | | | | | | | | | When a label is parsed, check if there is type information available for the label. If so, check if the symbol is a function. If the symbol is a function and we are in thumb mode and no explicit thumb_func has been emitted, adjust the symbol data to indicate that the function definition is a thumb function. The application of this inferencing is improved value handling in the object file (the required thumb bit is set on symbols which are thumb functions). It also helps improve compatibility with binutils. The one complication that arises from this handling is the MCAsmStreamer. The default implementation of getOrCreateSymbolData in MCStreamer does not support tracking the symbol data. In order to support the semantics of thumb functions, track symbol data in assembly streamer. Although O(n) in number of labels in the TU, this is already done in various other streamers and as such the memory overhead is not a practical concern in this scenario. llvm-svn: 204544
* Reapply 'ARM IAS: support .thumb_set'Saleem Abdulrasool2014-03-201-0/+70
| | | | | | | Re-apply the change after it was reverted to do conflicts due to another change being reverted. llvm-svn: 204306
* Revert "Add back r203962, r204028 and r204059."Rafael Espindola2014-03-191-70/+0
| | | | | | This reverts commit r204178. llvm-svn: 204203
* Add back r203962, r204028 and r204059.Rafael Espindola2014-03-181-0/+70
| | | | | | | | This reverts commit r204137. This includes a fix for handling aliases of aliases. llvm-svn: 204178
* Revert r203962 and two revisions depending on it: r204028 and r204059.Alexander Kornienko2014-03-181-70/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The revision I'm reverting breaks handling of transitive aliases. This blocks us and breaks sanitizer bootstrap: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/2651 (and checked locally by Alexey). This revision is the result of: svn merge -r204059:204058 -r204028:204027 -r203962:203961 . + the regression test added to test/MC/ELF/alias.s Another way to reproduce the regression with clang: $ cat q.c void a1(); void a2() __attribute__((alias("a1"))); void a3() __attribute__((alias("a2"))); void a1() {} $ ~/work/llvm-build/bin/clang-3.5-good -c q.c && mv q.o good.o && \ ~/work/llvm-build/bin/clang-3.5-bad -c q.c && mv q.o bad.o && \ objdump -t good.o bad.o good.o: file format elf64-x86-64 SYMBOL TABLE: 0000000000000000 l df *ABS* 0000000000000000 q.c 0000000000000000 l d .text 0000000000000000 .text 0000000000000000 l d .data 0000000000000000 .data 0000000000000000 l d .bss 0000000000000000 .bss 0000000000000000 l d .comment 0000000000000000 .comment 0000000000000000 l d .note.GNU-stack 0000000000000000 .note.GNU-stack 0000000000000000 l d .eh_frame 0000000000000000 .eh_frame 0000000000000000 g F .text 0000000000000006 a1 0000000000000000 g F .text 0000000000000006 a2 0000000000000000 g F .text 0000000000000006 a3 bad.o: file format elf64-x86-64 SYMBOL TABLE: 0000000000000000 l df *ABS* 0000000000000000 q.c 0000000000000000 l d .text 0000000000000000 .text 0000000000000000 l d .data 0000000000000000 .data 0000000000000000 l d .bss 0000000000000000 .bss 0000000000000000 l d .comment 0000000000000000 .comment 0000000000000000 l d .note.GNU-stack 0000000000000000 .note.GNU-stack 0000000000000000 l d .eh_frame 0000000000000000 .eh_frame 0000000000000000 g F .text 0000000000000006 a1 0000000000000000 g F .text 0000000000000006 a2 0000000000000000 g .text 0000000000000000 a3 llvm-svn: 204137
* ARM: add an assertionSaleem Abdulrasool2014-03-181-0/+1
| | | | | | | Add an assertion that a valid section is referenced. The potential NULL pointer dereference was identified by the clang static analyzer. llvm-svn: 204114
* ARM IAS: support .thumb_setSaleem Abdulrasool2014-03-171-0/+70
| | | | | | | | | | | | | | This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol or value which may possibly be yet undefined. This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does. The current implementation fails one test due to an unrelated issue. Functions within .thumb sections are not marked as thumb_func. The result is that the aliasee function is not valued correctly. llvm-svn: 204059
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-17/+19
| | | | | | class. llvm-svn: 203439
* Remove dead 'break' (dominated by 'return').Ted Kremenek2014-03-071-1/+0
| | | | llvm-svn: 203267
* ARM: Make .unreq directives case-insensitiveDuncan P. N. Exon Smith2014-03-071-1/+1
| | | | | | | | Be case-insensitive when processing .unreq directives. Patch by Lin Zuojian! llvm-svn: 203251
* ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) ↵Artyom Skrobov2014-02-261-0/+4
| | | | | | wouldn't affect CPSR in an IT block llvm-svn: 202257
* ARMAsmParser: whitespaceSaleem Abdulrasool2014-02-231-4/+4
| | | | llvm-svn: 201989
* ARM IAS: support .align without parametersSaleem Abdulrasool2014-02-231-0/+20
| | | | | | | | .align is handled specially on certain targets. .align without any parameters on ARM indicates a default alignment (4). Handle the special case in the target parser, but fall back to the generic parser for the normal version. llvm-svn: 201988
* ARM IAS: support .short and .hwordSaleem Abdulrasool2014-02-231-5/+9
| | | | | | | | This adds support for the .short and its alias .hword for adding literal values into the object file. This is similar to the .word directive, however, rather than inserting a value of 4 bytes, adds a 2-byte value. llvm-svn: 201968
* Remove unnecessary copy of array_lengthof.Benjamin Kramer2014-02-201-5/+2
| | | | llvm-svn: 201798
* Fix the arm assembler so that this malformed instruction:Kevin Enderby2014-02-171-1/+2
| | | | | | | | | | | | | | | | | | ldrd r6, r7 [r2, #15] simply gives an error and does not triggers an assertion. As Jim points out, the diagnostic is really strange here, but fixing that would be more complicated. The missing comma results in the parser expecting a construct like r2[2], which is the vector index thing the error message is talking about. That's not what the user intended, though, and there's nothing else in the instruction that looks at all like a vector. Yet more fallout from not having a real parser here and trying to do context-free generic matching for addressing modes. rdar://15097243 llvm-svn: 201531
* ARM IAS: (partially) support .arch_extension directiveSaleem Abdulrasool2014-02-161-0/+82
| | | | | | | | | | | | This adds a partial implementation of the .arch_extension directive to the integrated ARM assembler. There are a number of limitations to this implementation arising from the target backend support rather than the implementation itself. Namely, iWMMXT (v1 and v2), Maverick, and XScale support is not present in the ARM backend. Currently, there is no check for A-class only (needed for virt), and no ARMv6k detection (needed for os and sec). The remainder of the extensions are fully supported. llvm-svn: 201471
* Use the default values.Rafael Espindola2014-02-041-2/+2
| | | | llvm-svn: 200781
* Fix PR18345: ldr= pseudo instruction produces incorrect code when using in ↵David Peixotto2014-02-041-102/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | inline assembly This patch fixes the ldr-pseudo implementation to work when used in inline assembly. The fix is to move arm assembler constant pools from the ARMAsmParser class to the ARMTargetStreamer class. Previously we kept the assembler generated constant pools in the ARMAsmParser object. This does not work for inline assembly because a new parser object is created for each blob of inline assembly. This patch moves the constant pools to the ARMTargetStreamer class so that the constant pool will remain alive for the entire code generation process. An ARMTargetStreamer class is now required for the arm backend. There was no existing implementation for MachO, only Asm and ELF. Instead of creating an empty MachO subclass, we decided to make the ARMTargetStreamer a non-abstract class and provide default (llvm_unreachable) implementations for the non constant-pool related methods. Differential Revision: http://llvm-reviews.chandlerc.com/D2638 llvm-svn: 200777
* ARM IAS: support .object_archSaleem Abdulrasool2014-01-301-0/+42
| | | | | | | | | | The .object_arch directive indicates an alternative architecture to be specified in the object file. The directive does *not* effect the enabled feature bits for the object file generation. This is particularly useful when the code performs runtime detection and would like to indicate a lower architecture as the requirements than the actual instructions used. llvm-svn: 200451
* ARM IAS: support .movspSaleem Abdulrasool2014-01-301-3/+69
| | | | | | | | .movsp is an ARM unwinding directive that indicates to the unwinder that a register contains an offset from the current stack pointer. If the offset is unspecified, it defaults to zero. llvm-svn: 200449
* ARM: suuport .tlsdescseq directiveSaleem Abdulrasool2014-01-301-0/+27
| | | | | | | | | | | This enhances the ARMAsmParser to handle .tlsdescseq directives. This is a slightly special relocation. We must be able to generate them, but not consume them in assembly. The relocation is meant to assist the linker in generating a TLS descriptor sequence. The ELF target streamer is enhanced to append additional fixups into the current segment and that is used to emit the new R_ARM_TLS_DESCSEQ relocations. llvm-svn: 200448
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+1
| | | | llvm-svn: 200345
* ARM: improve diagnostics for .word directiveSaleem Abdulrasool2014-01-261-1/+3
| | | | | | | | | If a complex expression was passed to the .word directive and the first part of the directive failed to parse, a secondary diagnostic would be produced that would clutter the error diagnostics. Improve the diagnostics by consuming the remainder of the statement. llvm-svn: 200160
* InitToTextSection is redundant with InitSections. Remove it.Rafael Espindola2014-01-231-1/+1
| | | | llvm-svn: 199955
* [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForITWeiming Zhao2014-01-231-1/+1
| | | | | | | | | Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928
* ARM IAS: add support for .unwind_raw directiveSaleem Abdulrasool2014-01-211-0/+84
| | | | | | | | | | | | This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! llvm-svn: 199707
* ARM IAS: support .personalityindexSaleem Abdulrasool2014-01-211-3/+88
| | | | | | | | | | | | | The .personalityindex directive is equivalent to the .personality directive with the ARM EABI personality with the specific index (0, 1, 2). Both of these directives indicate personality routines, so enhance the personality directive handling to take into account personalityindex. Bonus fix: flush the UnwindContext at the beginning of a new function. Thanks to Logan Chien for additional tests! llvm-svn: 199706
* Move ARM build attributes into SupportSaleem Abdulrasool2014-01-191-1/+1
| | | | | | | | | | | | This moves the ARM build attributes definitions and support routines into the Support library. The support routines simply permit the conversion of the value to and from a string representation. The movement is prompted in order to permit access to the constants and string representations from readobj in order to facilitate decoding of the attributes section. llvm-svn: 199575
* ARM IAS: remove unnecessary special caseSaleem Abdulrasool2014-01-191-1/+1
| | | | | | | Tag_nodefaults is even and greater than 32 and thus does not need the special check to fall into the correct category. llvm-svn: 199574
* Make getTargetStreamer return a possibly null pointer.Rafael Espindola2014-01-141-1/+1
| | | | | | | | | This will allow it to be called from target independent parts of the main streamer that don't know if there is a registered target streamer or not. This in turn will allow targets to perform extra actions at specified points in the interface: add extra flags for some labels, extra work during finalization, etc. llvm-svn: 199174
* correct target directive handling error handlingSaleem Abdulrasool2014-01-131-24/+44
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. llvm-svn: 199068
* ARM IAS: fix diagnostics of improper qualificationSaleem Abdulrasool2014-01-121-0/+1
| | | | | | | | An improper qualifier would result in a superfluous error due to the parser not consuming the remainder of the statement. Simply consume the remainder of the statement to avoid the error. llvm-svn: 199035
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-121-0/+36
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
* ARM IAS: support #:{lower,upper}16: for GNU compatibilitySaleem Abdulrasool2014-01-101-0/+4
| | | | | | | | The GNU assembler supports prefixing the expression with a '#' to indiciate that the value that is being moved is infact a constant. This improves the compatibility of the integrated assembler's parser for this. llvm-svn: 198916
* ARM IAS: support GNU extension for ldrd, strdSaleem Abdulrasool2014-01-101-0/+18
| | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. llvm-svn: 198915
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-081-6/+18
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-071-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. llvm-svn: 198697
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