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* MC: Remove MCSubtargetInfo::InitCPUSched()Duncan P. N. Exon Smith2015-07-101-1/+0
| | | | | | | | | | | | Remove all calls to `MCSubtargetInfo::InitCPUSched()` and merge its body into the only relevant caller, `MCSubtargetInfo::InitMCProcessorInfo()`. We were only calling the former after explicitly calling the latter with the same CPU; it's confusing to have both methods exposed. Besides a minor (surely unmeasurable) speedup in ARM and X86 from avoiding running the logic twice, no functionality change. llvm-svn: 241956
* [ARM] Thumb1 3 to 2 operand convertion for commutative operationsScott Douglass2015-07-091-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D11057 llvm-svn: 241802
* [ARM] Don't be overzealous converting Thumb1 3 to 2 operandsScott Douglass2015-07-091-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D11056 llvm-svn: 241801
* [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2Scott Douglass2015-07-091-2/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11055 llvm-svn: 241800
* [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)Scott Douglass2015-07-091-42/+45
| | | | | | | | Also adds some test cases. Differential Revision: http://reviews.llvm.org/D11054 llvm-svn: 241799
* Reverting r241058 because it's causing buildbot failures.Ranjeet Singh2015-06-301-26/+26
| | | | llvm-svn: 241061
* There are a few places where subtarget features are stillRanjeet Singh2015-06-301-26/+26
| | | | | | | | | represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 llvm-svn: 241058
* Change .thumb_set to have the same error checks as .set.Pete Cooper2015-06-221-14/+6
| | | | | | | | | | | | | | According to the documentation, .thumb_set is 'the equivalent of a .set directive'. We didn't have equivalent behaviour in terms of all the errors we could throw, for example, when a symbol is redefined. This change refactors parseAssignment so that it can be used by .set and .thumb_set and implements tests for .thumb_set for all the errors thrown by that method. Reviewed by Rafael Espíndola. llvm-svn: 240318
* Fix "the the" in comments.Eric Christopher2015-06-191-1/+1
| | | | llvm-svn: 240112
* Removing spurious semi colons; NFC.Aaron Ballman2015-06-091-1/+1
| | | | llvm-svn: 239399
* [ARM] Add knowledge of FPU subtarget features to TargetParserJohn Brawn2015-06-051-67/+5
| | | | | | | | | | | | | Add getFPUFeatures to TargetParser, which gets the list of subtarget features that are enabled/disabled for each FPU, and use it when handling the .fpu directive. No functional change in this commit, though clang will start behaving differently once it starts using this. Differential Revision: http://reviews.llvm.org/D10237 llvm-svn: 239150
* Comment change. NFCRenato Golin2015-05-301-3/+2
| | | | | | | That comment misleads the current discussions in mentioned bug. Leave the discussions to the bug. Also, adding a future change FIXME. llvm-svn: 238653
* [ARMTargetParser] Move IAS arch ext parser. NFCRenato Golin2015-05-301-20/+22
| | | | | | | | | | | The plan was to move the whole table into the already existing ArchExtNames but some fields depend on a table-generated file, and we don't yet have this feature in the generic lib/Support side. Once the minimum target-specific table-generated files are available in a generic fashion to these libraries, we'll have to keep it in the ASM parser. llvm-svn: 238651
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-14/+14
| | | | llvm-svn: 238634
* Use operator<< instead of print in a few more places.Rafael Espindola2015-05-271-1/+1
| | | | llvm-svn: 238315
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-77/+79
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-4/+4
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-269/+269
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-79/+77
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-77/+79
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Change TargetParser enum names to avoid macro conflicts (llvm)Renato Golin2015-05-121-16/+16
| | | | | | | | | sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1" using a cpp macro. The result is that this fails to compile. Fixes https://llvm.org/PR23482 llvm-svn: 237112
* TargetParser: FPU/ARCH/EXT parsing refactory - NFCRenato Golin2015-05-081-22/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new class in a global context contain arch-specific knowledge in order to provide LLVM libraries, tools and projects with the ability to understand the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are supported. Current behaviour it to parse from free-text to enum values and back, so that all users can share the same parser and codes. This simplifies a lot both the ASM/Obj streamers in the back-end (where this came from), and the front-end parsers for command line arguments (where this is going to be used next). The previous implementation, using .def/.h includes is deprecated due to its inflexibility to be built without the backend support and for being too cumbersome. As more architectures join this scheme, and as more features of such architectures are added (such as hardware features, type sizes, etc) into a full blown TargetDescription class, having a set of classes is the most sane implementation. The ultimate goal of this refactor both LLVM's and Clang's target description classes into one unique interface, so that we can de-duplicate and standardise the descriptions, as well as make it available for other front-ends, tools, etc. The FPU parsing for command line options in Clang has been converted to use this new library and a number of aliases were added for compatibility: * A bogus neon-vfpv3 alias (neon defaults to vfp3) * armv5/v6 * {fp4/fp5}-{sp/dp}-d16 Next steps: * Port Clang's ARCH/EXT parsing to use this library. * Create a TableGen back-end to generate this information. * Run this TableGen process regardless of which back-ends are built. * Expose more information and rename it to TargetDescription. * Continue re-factoring Clang to use as much of it as possible. llvm-svn: 236900
* [ARM] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-161-1/+1
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
* Fix BXJ is undefined in AArch32.Charlie Turner2015-04-151-0/+8
| | | | | | | | | | | | | | BXJ was incorrectly said to be unsupported in ARMv8-A. It is not supported in the A64 instruction set, but it is supported in the T32 and A32 instruction sets, because it's listed as an instruction in the ARM ARM section F7.1.28. Using SP as an operand to BXJ changed from UNPREDICTABLE to PREDICTABLE in v8-A. This patch reflects that update as well. This was found by MCHammer. llvm-svn: 235024
* Refactor: Simplify boolean expressions in ARM targetAlexander Kornienko2015-04-141-27/+24
| | | | | | | | | | Simplify boolean expressions using `true` and `false` with `clang-tidy` http://reviews.llvm.org/D8524 Patch by Richard Thomson! llvm-svn: 234901
* [ARM] Rename v8.1a from "extension" to "architecture"Vladimir Sukharev2015-04-011-2/+2
| | | | | | | | | | | | | | v8.1a is renamed to architecture, following current entity naming approach. Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8767 llvm-svn: 233811
* [AArch64, ARM] Add v8.1a architecture and generic cpuVladimir Sukharev2015-03-261-0/+3
| | | | | | | | | | | | New architecture and cpu added, following http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8505 llvm-svn: 233290
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-79/+77
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-77/+79
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Fix uses of reserved identifiers starting with an underscore followed by an ↵David Blaikie2015-03-161-3/+3
| | | | | | | | | uppercase letter This covers essentially all of llvm's headers and libs. One or two weird cases I wasn't sure were worth/appropriate to fix. llvm-svn: 232394
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-79/+77
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-77/+79
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* ARM: Fix another regression introduced in r223113Asiri Rathnayake2015-02-121-5/+0
| | | | | | | | | | | | | | | | | | | | | The changes in r223113 (ARM modified-immediate syntax) have broken instructions like: mov r0, #~0xffffff00 The problem is that I've added a spurious range check on the immediate operand to ensure that it lies between INT32_MIN and UINT32_MAX. While this range check is correct in theory, it causes problems because the operand is stored in an int64_t (by MC). So valid 32-bit constants like \#~0xffffff00 become out of range. The solution is to simply remove this range check. It is not possible to validate the range of the immediate operand with the current setup because: 1) The operand is stored in an int64_t by MC, 2) The immediate can be of the forms #imm, #-imm, #~imm or even #((~imm)) etc. So we just chop the value to 32 bits and use it. Also noted that the original range check was note tested by any of the unit tests. I've added a new test to cover #~imm kind of operands. Change-Id: I411e90d84312a2eff01b732bb238af536c4a7599 llvm-svn: 228920
* [ARM] Fix subtarget feature set truncation when using .cpu directiveBradley Smith2015-02-041-2/+1
| | | | | | | This is a bug that was caused due to storing the feature bitset in a 32-bit variable when it is a 64-bit mask, discarding the top half of the feature set. llvm-svn: 228151
* Fix some unnoticed/unwanted behavior change from r222319.Frederic Riss2015-02-041-1/+1
| | | | | | | | | The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. llvm-svn: 228109
* ARM: make a table more readable (NFC)Saleem Abdulrasool2015-01-311-28/+40
| | | | | | | | This adds some comments and splits the flag calculation on type boundaries to make the table more readable. Addresses some post-commit review comments to SVN r227603. NFC. llvm-svn: 227670
* ARM: further correct .fpu directive handlingSaleem Abdulrasool2015-01-301-7/+9
| | | | | | | | | | If the original FPU specification involved a restricted VFP unit (d16), ensure that we reset the functionality when we encounter a new FPU type. In particular, if the user specified vfpv3-d16, but switched to a VFPv3 (which has 32 double precision registers), we would fail to reset the D16 feature, and treat it as being equivalent to vfpv3-d16. llvm-svn: 227603
* ARM: improve caret diagnostics for invalid FPU nameSaleem Abdulrasool2015-01-301-1/+2
| | | | | | | In the case of an invalid FPU name, place the caret at the name rather than FPU directive. llvm-svn: 227595
* ARM: correct handling of .fpu directiveSaleem Abdulrasool2015-01-301-23/+35
| | | | | | | | | | | | | The FPU directive permits the user to switch the target FPU, enabling instructions that would be otherwise unavailable. However, when configuring the new subtarget features, we would not enable the implied functions for newer FPUs. This would result in invalid rejection of valid input. Ensure that we inherit the implied FPU functionality when enabling newer versions of the FPU. Fortunately, these are mostly hierarchical, unlike the CPUs. Addresses PR22395. llvm-svn: 227584
* Correct POP handling for v7mJyoti Allur2015-01-141-4/+4
| | | | llvm-svn: 225972
* ARM: prepare prefix parsing for improved AAELF supportSaleem Abdulrasool2015-01-131-5/+43
| | | | | | | | AAELF specifies a number of ELF specific relocation types which have custom prefixes for the symbol reference. Switch the parser to be more table driven with an idea of file formats for which they apply. NFC. llvm-svn: 225758
* Fix regression in r225266.Asiri Rathnayake2015-01-071-1/+1
| | | | | | | | The change in r225266 was reviewed under D6722. But the commit r225266 has a typo, causing some MCHammer failures. This patch fixes it. Change-Id: I573efcff25003af7478ac02548ebbe929fc7f5fd llvm-svn: 225347
* [ARM] Cleanup so_imm* tblgen defintionsAsiri Rathnayake2015-01-061-41/+8
| | | | | | | | | | | No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
* Parse Tag_compatibility correctly.Charlie Turner2015-01-051-2/+7
| | | | | | | | Tag_compatibility takes two arguments, but before this patch it would erroneously accept just one, it now produces an error in that case. Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d llvm-svn: 225167
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-1/+0
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* ARM: fix an off-by-one in the register list accessSaleem Abdulrasool2014-12-181-2/+2
| | | | | | | | | Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-181-15/+76
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* Fix modified immediate bug reported by MC Hammer.Asiri Rathnayake2014-12-091-11/+6
| | | | | | | | | | | | | Instructions of the form [ADD Rd, pc, #imm] are manually aliased in processInstruction() to use ADR. To accomodate this, mod_imm handling had to be tweaked a bit. Turns out it was the manual aliasing that must be tweaked to accommodate mod_imms instead. More information about the parsed instruction is available at the point where processInstruction() is invoked, which makes it easier to detect a mod_imm at that point rather than trying to detect a potential alias when a mod_imm is being prepped. Added a test case and fixed some white spaces as well. llvm-svn: 223772
* Add a FIXME as requested by Renato Golin.Roman Divacky2014-12-041-0/+3
| | | | llvm-svn: 223390
* Fix yet another unseen regression caused by r223113Asiri Rathnayake2014-12-041-14/+26
| | | | | | | | | | r223113 added support for ARM modified immediate assembly syntax. Which assumes all immediate operands are prefixed with a '#'. This assumption is wrong as per the ARMARM - which recommends that all '#' characters be treated optional. The current patch fixes this regression and adds a test case. A follow-up patch will expand the test coverage to other instructions. llvm-svn: 223381
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