summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/AsmParser
Commit message (Collapse)AuthorAgeFilesLines
...
* Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton2012-06-271-1/+2
| | | | | | instruction llvm-svn: 159257
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-221-1/+9
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-151-11/+11
| | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-1/+2
| | | | llvm-svn: 158445
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-4/+4
| | | | llvm-svn: 157885
* Mark a static array as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157368
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-171-4/+29
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-111-1/+3
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-271-0/+20
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-1/+1
| | | | llvm-svn: 155720
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-271-5/+2
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-251-2/+9
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-251-0/+1
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-3/+16
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* ARM handle :lower16: and :upper16: after a '#' prefix.Jim Grosbach2012-04-161-13/+17
| | | | | | rdar://11252521 llvm-svn: 154862
* Wire up support for diagnostic ranges in the ARMAsmParser.Benjamin Kramer2012-04-151-3/+12
| | | | | | | | | | | | | | As an example, attach range info to the "invalid instruction" message: $ clang -arch arm -c asm.c asm.c:2:11: error: invalid instruction __asm__("foo r0"); ^ <inline asm>:1:2: note: instantiated into assembly here foo r0 ^~~ llvm-svn: 154765
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+31
| | | | | | rdar://11222742 llvm-svn: 154457
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+2
| | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-2/+5
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 llvm-svn: 154411
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+38
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 llvm-svn: 154123
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-1/+2
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 llvm-svn: 154080
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-4/+6
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. llvm-svn: 153770
* ARM can only use narrow encoding for low regs.Jim Grosbach2012-03-301-0/+1
| | | | llvm-svn: 153765
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+25
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 llvm-svn: 153759
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-301-3/+3
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 llvm-svn: 153753
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-291-2/+4
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 llvm-svn: 153689
* Prune some includesCraig Topper2012-03-271-2/+0
| | | | llvm-svn: 153502
* Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby2012-03-201-1/+1
| | | | llvm-svn: 153099
* ARM assembly, accept optional '#' on lane index number.Jim Grosbach2012-03-191-0/+6
| | | | | | rdar://11057160 llvm-svn: 153053
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-2/+6
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
* Remove inadvertant commit.Jim Grosbach2012-03-151-23/+0
| | | | llvm-svn: 152870
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-152-3/+28
| | | | | | rdar://11056591 llvm-svn: 152846
* ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach2012-03-151-1/+1
| | | | | | rdar://11056647 llvm-svn: 152834
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-8/+5
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-5/+13
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-10/+14
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM Remove a bit of dead code.Jim Grosbach2012-03-051-5/+0
| | | | llvm-svn: 152061
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+24
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-4/+4
| | | | llvm-svn: 149961
* Tidy up. One more return type mismatch fix.Jim Grosbach2012-01-311-1/+1
| | | | llvm-svn: 149452
* Keep source information, if available, around for ARM Fixups.Jim Grosbach2012-01-261-0/+1
| | | | | | | | | | | | | | | | | Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 llvm-svn: 149093
* Tidy up. Fix mismatched return types for error handling.Jim Grosbach2012-01-261-8/+4
| | | | llvm-svn: 149062
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-3/+10
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-1/+108
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+101
| | | | llvm-svn: 148882
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+99
| | | | llvm-svn: 148836
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+145
| | | | llvm-svn: 148832
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+97
| | | | llvm-svn: 148764
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+97
| | | | llvm-svn: 148762
* Tidy up. Remove some vertical space for readability.Jim Grosbach2012-01-241-344/+121
| | | | llvm-svn: 148761
OpenPOWER on IntegriCloud