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* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-2/+6
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
* Remove inadvertant commit.Jim Grosbach2012-03-151-23/+0
| | | | llvm-svn: 152870
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-152-3/+28
| | | | | | rdar://11056591 llvm-svn: 152846
* ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach2012-03-151-1/+1
| | | | | | rdar://11056647 llvm-svn: 152834
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-8/+5
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-5/+13
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-10/+14
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM Remove a bit of dead code.Jim Grosbach2012-03-051-5/+0
| | | | llvm-svn: 152061
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+24
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-4/+4
| | | | llvm-svn: 149961
* Tidy up. One more return type mismatch fix.Jim Grosbach2012-01-311-1/+1
| | | | llvm-svn: 149452
* Keep source information, if available, around for ARM Fixups.Jim Grosbach2012-01-261-0/+1
| | | | | | | | | | | | | | | | | Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 llvm-svn: 149093
* Tidy up. Fix mismatched return types for error handling.Jim Grosbach2012-01-261-8/+4
| | | | llvm-svn: 149062
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-3/+10
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-1/+108
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+101
| | | | llvm-svn: 148882
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+99
| | | | llvm-svn: 148836
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+145
| | | | llvm-svn: 148832
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+97
| | | | llvm-svn: 148764
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+97
| | | | llvm-svn: 148762
* Tidy up. Remove some vertical space for readability.Jim Grosbach2012-01-241-344/+121
| | | | llvm-svn: 148761
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-241-0/+126
| | | | llvm-svn: 148755
* NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-20/+147
| | | | llvm-svn: 148748
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-6/+138
| | | | llvm-svn: 148745
* NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach2012-01-231-0/+164
| | | | llvm-svn: 148734
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-263/+96
| | | | | | | Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
* Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.Jim Grosbach2012-01-211-1/+3
| | | | llvm-svn: 148601
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-6/+1
| | | | llvm-svn: 148578
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-36/+32
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach2012-01-191-3/+4
| | | | llvm-svn: 148459
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+39
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-161-6/+0
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+26
| | | | | | rdar://10558523 llvm-svn: 147189
* Tidy up. Use predicate function a bit more liberally.Jim Grosbach2011-12-221-97/+52
| | | | llvm-svn: 147184
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-221-1/+1
| | | | llvm-svn: 147158
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+33
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 llvm-svn: 147153
* ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach2011-12-221-0/+4
| | | | llvm-svn: 147152
* Tidy up. Trailing whitespace.Jim Grosbach2011-12-221-2/+2
| | | | llvm-svn: 147151
* Nuke invalid comment from copy/paste.Jim Grosbach2011-12-221-1/+0
| | | | llvm-svn: 147150
* ARM asm parser should be more lenient w/ .thumb_func directive.Jim Grosbach2011-12-211-8/+17
| | | | | | | | | | Rather than require the symbol to be explicitly an argument of the directive, allow it to look ahead and grab the symbol from the next non-whitespace line. rdar://10611140 llvm-svn: 147100
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-211-1/+3
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 llvm-svn: 147096
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-211-0/+36
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 llvm-svn: 147094
* ARM assembly parsing allows constant expressions for lane indices.Jim Grosbach2011-12-211-14/+25
| | | | llvm-svn: 147028
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-4/+20
| | | | llvm-svn: 147025
* ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach2011-12-201-3/+4
| | | | llvm-svn: 147009
* Move comment to appropriate place.Jim Grosbach2011-12-201-1/+1
| | | | llvm-svn: 147000
* ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach2011-12-201-37/+113
| | | | llvm-svn: 146990
* ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach2011-12-201-42/+134
| | | | llvm-svn: 146983
* First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim2011-12-201-0/+18
| | | | | | | (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) llvm-svn: 146977
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