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* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-201-0/+17
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 llvm-svn: 146937
* ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach2011-12-191-0/+30
| | | | | | | | e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 llvm-svn: 146925
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-0/+29
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-191-1/+3
| | | | llvm-svn: 146892
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-191-1/+1
| | | | llvm-svn: 146887
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-191-2/+5
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. llvm-svn: 146884
* Silence warning.Jim Grosbach2011-12-151-1/+1
| | | | llvm-svn: 146686
* ARM NEON two-register double spaced register list parsing support.Jim Grosbach2011-12-151-14/+49
| | | | llvm-svn: 146685
* ARM NEON better assembly operand range checking for lane indices of VLD/VST.Jim Grosbach2011-12-141-0/+20
| | | | llvm-svn: 146608
* ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach2011-12-141-192/+349
| | | | llvm-svn: 146605
* ARM assembler support for the target-specific .req directive.Jim Grosbach2011-12-141-1/+67
| | | | | | rdar://10549683 llvm-svn: 146543
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-131-1/+38
| | | | | | rdar://10549767 llvm-svn: 146520
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-131-0/+8
| | | | | | rdar://10550269 llvm-svn: 146519
* Thumb2 tweak for ccout handling in RSB parsing.Jim Grosbach2011-12-131-1/+4
| | | | llvm-svn: 146516
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-131-2/+8
| | | | | | rdar://10549741 llvm-svn: 146515
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-131-0/+1
| | | | llvm-svn: 146508
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
| | | | llvm-svn: 146409
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-101-1/+1
| | | | llvm-svn: 146300
* ARM add some pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-091-0/+9
| | | | llvm-svn: 146296
* ARM allows '' syntax, not just '#imm' for assembly.Jim Grosbach2011-12-091-10/+21
| | | | | | | | Backwards compatibility with 'gas'. #imm is the preferered and documented syntax, but lots of existing code uses the '$' prefix, so we should support it if we can. llvm-svn: 146285
* ARM convenience aliases for VSQRT.Jim Grosbach2011-12-081-1/+1
| | | | llvm-svn: 146201
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-081-0/+32
| | | | llvm-svn: 146192
* ARM asm parser, just issue a warning for a duplicate reg in a list.Jim Grosbach2011-12-081-1/+7
| | | | | | For better 'gas' compatibility. llvm-svn: 146185
* ARM assembler support for register name aliases.Jim Grosbach2011-12-081-2/+16
| | | | | | rdar://10550084 llvm-svn: 146170
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-081-0/+8
| | | | llvm-svn: 146125
* ARM VFP support 'fmrs/fmsr' aliases for 'vldr'Jim Grosbach2011-12-081-0/+1
| | | | llvm-svn: 146116
* ARM VFP support 'flds/fldd' aliases for 'vldr'Jim Grosbach2011-12-081-1/+1
| | | | llvm-svn: 146115
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-081-0/+32
| | | | llvm-svn: 146111
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-071-1/+3
| | | | | | For 'gas' compatibility. llvm-svn: 146106
* ARM support the .arm and .thumb directives for assembly mode switching.Jim Grosbach2011-12-071-3/+19
| | | | llvm-svn: 146042
* ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach2011-12-071-0/+48
| | | | llvm-svn: 146003
* Thumb2 encoding choice correction for PLD.Jim Grosbach2011-12-061-2/+2
| | | | | | | | Using encoding T1 for offset of #0 and encoding T2 for #-0. rdar://10532413 llvm-svn: 145919
* Tweak ADDrr fix. Bad check for explicit .wJim Grosbach2011-12-051-2/+2
| | | | llvm-svn: 145863
* Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach2011-12-051-0/+20
| | | | | | rdar://10529664 llvm-svn: 145860
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-051-0/+18
| | | | | | rdar://10529348 llvm-svn: 145851
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-021-0/+16
| | | | llvm-svn: 145726
* ARM VST1 single lane assembly parsing.Jim Grosbach2011-12-021-4/+150
| | | | llvm-svn: 145718
* ARM VLD1 single lane assembly parsing.Jim Grosbach2011-12-021-5/+101
| | | | llvm-svn: 145712
* Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach2011-12-021-4/+32
| | | | | | Add the 16-bit lane variants while I'm at it. llvm-svn: 145693
* ARM start parsing VLD1 single lane instructions.Jim Grosbach2011-12-021-14/+97
| | | | | | | The alias pseudos need cleaned up for size suffix handling, but this gets the basics working. Will be cleaning up and adding more. llvm-svn: 145655
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+5
| | | | llvm-svn: 145504
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-3/+114
| | | | llvm-svn: 145464
* Tidy up a bit.Jim Grosbach2011-11-291-33/+5
| | | | llvm-svn: 145458
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-291-8/+0
| | | | llvm-svn: 145420
* Clean up debug printing of ARM shifted operands.Jim Grosbach2011-11-161-9/+6
| | | | llvm-svn: 144836
* ARM assembly parsing for RRX mnemonic.Jim Grosbach2011-11-161-1/+14
| | | | | | rdar://9704684 llvm-svn: 144812
* ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach2011-11-161-0/+26
| | | | | | rdar://9704684 llvm-svn: 144803
* ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach2011-11-151-2/+34
| | | | | | | | | | | | | | | | For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 llvm-svn: 144727
* ARM accept an immediate offset in memory operands w/o the '#'.Jim Grosbach2011-11-151-3/+6
| | | | llvm-svn: 144709
* ARM enclosing curly braces optional on one-register VLD/VST instruction lists.Jim Grosbach2011-11-151-2/+23
| | | | | | | | 'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]' rdar://10450488. llvm-svn: 144701
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