summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMTargetMachine.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+5
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-131-1/+1
| | | | llvm-svn: 163803
* Consistently use AnalysisID types in TargetPassConfig.Bob Wilson2012-07-021-2/+2
| | | | | | | This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. llvm-svn: 159568
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-10/+10
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-10/+10
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* Preserve implicit defs in ARMLoadStoreOptimizer.Jakob Stoklund Olesen2012-03-281-1/+3
| | | | | | | | | | | When a number of sub-register VLRDS instructions are combined into a VLDM, preserve any super-register implicit defs. This is required to keep the register scavenger and machine code verifier happy. Enable machine code verification after ARMLoadStoreOptimizer. ARM/2012-01-26-CopyPropKills.ll was failing because of this. llvm-svn: 153610
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-2/+2
| | | | | | | | | | | | | Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). llvm-svn: 150100
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-041-6/+4
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. llvm-svn: 149754
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-031-18/+46
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. llvm-svn: 149672
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+5
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+8
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-5/+9
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-23/+20
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cppDevang Patel2011-10-171-1/+2
| | | | | | There is no reason to have simple IR level pass in lib/Target. llvm-svn: 142200
* Add a natural stack alignment field to TargetData, and prevent InstCombine fromLang Hames2011-10-101-4/+11
| | | | | | | | | | | | | | promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. llvm-svn: 141599
* Use ExecutionDepsFix instead of NEONMoveFix.Jakob Stoklund Olesen2011-09-291-1/+1
| | | | | | | This enables NEON domain tracking across basic blocks, but should otherwise do the same thing. llvm-svn: 140772
* Move to ISelLowering.Bill Wendling2011-09-291-2/+0
| | | | llvm-svn: 140754
* Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.Bill Wendling2011-09-281-1/+1
| | | | llvm-svn: 140718
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-271-1/+3
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Hide -global-merge option.Evan Cheng2011-08-251-1/+1
| | | | llvm-svn: 138540
* Add a command line option to disable global merge pass.Evan Cheng2011-08-251-1/+6
| | | | llvm-svn: 138536
* Remove a out-of-place comment.Evan Cheng2011-08-251-1/+0
| | | | llvm-svn: 138534
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-33/+0
| | | | llvm-svn: 135825
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-6/+6
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-19/+12
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-14/+0
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+1
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-071-5/+4
| | | | | | ARM subtarget info available to MC. llvm-svn: 134569
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+6
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Remove TargetOptions.h dependency from ARMSubtarget.Evan Cheng2011-06-231-0/+4
| | | | llvm-svn: 133738
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-191-12/+11
| | | | | | predicates. llvm-svn: 129816
* This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson2011-04-191-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. llvm-svn: 129775
* Tidy up.Jim Grosbach2011-04-061-2/+1
| | | | llvm-svn: 129034
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-171-1/+0
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. llvm-svn: 125747
* Add support for the --noexecstack option.Rafael Espindola2011-01-231-2/+3
| | | | llvm-svn: 124077
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-5/+5
| | | | | | and fixes here and there. llvm-svn: 123170
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
* tidy upChris Lattner2010-11-171-18/+11
| | | | llvm-svn: 119462
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-3/+6
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Revert the accidental commit I made reverting the previous commit.Eric Christopher2010-11-111-6/+7
| | | | llvm-svn: 118835
* Revert this temporarily.Eric Christopher2010-11-111-7/+6
| | | | llvm-svn: 118827
* Jim Asked us to move DataLayout on ARM back to the most specialized classes. DoRafael Espindola2010-10-031-5/+16
| | | | | | | | so and also change X86 for consistency. Investigating if this can be improved a bit. llvm-svn: 115469
* I added a new file ARMAsmBackend which stubs out in similar ways toJason W Kim2010-09-301-0/+6
| | | | | | | | | | the eqv X86 class. For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend (also mimicking X86) Tested against -r115126 llvm-svn: 115129
* Resolve this GCC warning:Nick Lewycky2010-09-281-1/+2
| | | | | | ARMTargetMachine.cpp:53: error: control reaches end of non-void function llvm-svn: 114992
* Odd additional stub framework for the ARM MC ELF emission.Rafael Espindola2010-09-271-14/+39
| | | | | | | | | llc now recognizes the "intent" to support MC/obj emission for ARM, but given that they are all stubs, it asserts on --filetype=obj --march=arm Patch by Jason Kim. llvm-svn: 114856
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-3/+0
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-111-0/+3
| | | | | | support it. e.g. cortex-m* processors. llvm-svn: 110798
* Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable ↵Evan Cheng2010-08-091-7/+1
| | | | | | more 32-bit to 16-bit optimizations. llvm-svn: 110584
OpenPOWER on IntegriCloud