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path: root/llvm/lib/Target/ARM/ARMSubtarget.h
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* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-5/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-1/+7
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-181-0/+5
| | | | | | | | | contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. llvm-svn: 89187
* Allow target to specify regclass for which antideps will only be broken ↵David Goodwin2009-11-131-1/+1
| | | | | | along the critical path. llvm-svn: 88682
* Fixed to address code review. No functional changes.David Goodwin2009-11-101-8/+2
| | | | llvm-svn: 86634
* Allow targets to specify register classes whose member registers should not ↵David Goodwin2009-11-101-2/+6
| | | | | | be renamed to break anti-dependencies. llvm-svn: 86628
* Break anti-dependence breaking out into its own class.David Goodwin2009-10-261-1/+1
| | | | llvm-svn: 85127
* Allow the target to select the level of anti-dependence breaking that should ↵David Goodwin2009-10-221-1/+3
| | | | | | be performed by the post-RA scheduler. The default is none. llvm-svn: 84911
* Change createPostRAScheduler so it can be turned off at llc -O1.Evan Cheng2009-10-161-3/+5
| | | | llvm-svn: 84273
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-301-0/+7
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Reference to hidden symbols do not have to go through non-lazy pointer in ↵Evan Cheng2009-09-031-1/+2
| | | | | | non-pic mode. rdar://7187172. llvm-svn: 80904
* Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a ↵Evan Cheng2009-08-281-0/+5
| | | | | | bunch of nasty code in ARM asm printer. llvm-svn: 80404
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-4/+4
| | | | llvm-svn: 78666
* By default, for cortex-a8 use NEON for single-precision FP. David Goodwin2009-08-051-1/+3
| | | | llvm-svn: 78200
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-041-1/+6
| | | | | | to enable. Added patterns for some binary FP operations. llvm-svn: 78081
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-021-3/+2
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* isThumb2 really should mean thumb2 only, not thumb2+.Evan Cheng2009-07-061-1/+1
| | | | llvm-svn: 74871
* Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, ↵Evan Cheng2009-07-021-1/+2
| | | | | | not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. llvm-svn: 74692
* Revert 74164. We'll want to use this method later.Bob Wilson2009-06-251-0/+1
| | | | llvm-svn: 74176
* Remove unused hasV6T2Ops method. We already have a separate feature toBob Wilson2009-06-251-1/+0
| | | | | | identify Thumb2. llvm-svn: 74164
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ↵Evan Cheng2009-06-191-0/+8
| | | | | | we are only using branch latency to determine if-conversion limits. llvm-svn: 73747
* Remove UseThumbBacktraces. Just check if subtarget is darwin.Evan Cheng2009-06-181-4/+0
| | | | llvm-svn: 73734
* Rename methods for the sake of consistency.Anton Korobeynikov2009-06-151-2/+2
| | | | llvm-svn: 73428
* Separate V6 from V6T2 since the latter has some extra nice instructionsAnton Korobeynikov2009-06-081-1/+2
| | | | llvm-svn: 73085
* Add helper for checking of Thumb1 modeAnton Korobeynikov2009-06-081-0/+1
| | | | llvm-svn: 73080
* Implement review feedback. Make thumb2 'normal' subtarget featureAnton Korobeynikov2009-06-011-4/+6
| | | | llvm-svn: 72698
* Add placeholder for thumb2 stuffAnton Korobeynikov2009-05-291-5/+12
| | | | llvm-svn: 72593
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-231-11/+17
| | | | llvm-svn: 72337
* Propagate CPU string out of SubtargetFeaturesAnton Korobeynikov2009-05-231-2/+8
| | | | llvm-svn: 72335
* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into ↵Rafael Espindola2007-10-311-1/+5
| | | | | | | | | | getMaxInlineSizeThreshold and by restructuring the X86 version. New I just have to move this to a common place :-) llvm-svn: 43554
* Make ARM an X86 memcpy expansion more similar to each other.Rafael Espindola2007-10-311-0/+1
| | | | | | | | Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it. This should not change generated code. llvm-svn: 43552
* Added -march=thumb; removed -enable-thumb.Evan Cheng2007-02-231-1/+1
| | | | llvm-svn: 34521
* Add ABI information to ARM subtarget.Lauro Ramos Venancio2007-02-131-1/+9
| | | | llvm-svn: 34245
* Introduce TargetType's ELF and Darwin.Evan Cheng2007-01-191-3/+7
| | | | llvm-svn: 33363
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+82
llvm-svn: 33353
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