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* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-101-0/+4
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
* Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-211-1/+8
| | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. llvm-svn: 177651
* TypoRenato Golin2013-02-161-1/+1
| | | | llvm-svn: 175371
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-161-1/+3
| | | | | | new features. llvm-svn: 175336
* Temporary revert of 175320.Bill Wendling2013-02-151-3/+1
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-151-1/+3
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Support changing the subtarget features in ARM.Bill Wendling2013-02-151-0/+4
| | | | llvm-svn: 175315
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-0/+4
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* Add ARM cortex-r5 subtarget.Quentin Colombet2012-12-211-1/+2
| | | | llvm-svn: 170840
* On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng2012-12-201-0/+5
| | | | | | | | | are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 llvm-svn: 170728
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-041-1/+1
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-2/+2
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2012-11-291-1/+2
| | | | llvm-svn: 168933
* Add LLVM support for Swift.Bob Wilson2012-09-291-1/+11
| | | | llvm-svn: 164899
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-131-1/+3
| | | | llvm-svn: 163803
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-0/+3
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
* whitespaceAndrew Trick2012-08-081-1/+1
| | | | llvm-svn: 161469
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-3/+1
| | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-1/+1
| | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-051-2/+2
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> llvm-svn: 152036
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-0/+5
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-5/+0
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-0/+5
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-2/+6
| | | | | | Patch by Ana Pazos! llvm-svn: 148658
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-0/+1
| | | | llvm-svn: 146981
* Hide cpu name checking in ARMSubtarget.Evan Cheng2011-11-091-0/+1
| | | | llvm-svn: 144154
* Remove NaClModeDavid Meyer2011-10-181-3/+0
| | | | llvm-svn: 142338
* Reenable tail calls for iOS 5.0 and later.Bob Wilson2011-10-071-0/+6
| | | | llvm-svn: 141370
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-0/+6
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+6
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Rewrite comment in English.Evan Cheng2011-07-071-1/+1
| | | | llvm-svn: 134627
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-071-5/+5
| | | | llvm-svn: 134626
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-1/+2
| | | | llvm-svn: 134606
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-071-23/+24
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-071-11/+7
| | | | | | ARM subtarget info available to MC. llvm-svn: 134569
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-011-2/+7
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-3/+3
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+4
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+3
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-2/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Revert accidental commit.Evan Cheng2011-05-201-6/+0
| | | | llvm-svn: 131739
* Revert r131664 and fix it in instcombine instead. rdar://9467055Evan Cheng2011-05-201-0/+6
| | | | llvm-svn: 131708
* Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng2011-04-201-0/+2
| | | | llvm-svn: 129884
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-191-1/+1
| | | | | | predicates. llvm-svn: 129816
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-191-0/+6
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng2011-03-311-0/+5
| | | | | | | | | | | accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-111-3/+6
| | | | llvm-svn: 123276
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
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