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* Stop resetting NoFramePointerElim in TargetMachine::resetTargetOptions.Akira Hatanaka2015-05-231-0/+7
| | | | | | | | | | | | | | This is part of the work to remove TargetMachine::resetTargetOptions. In this patch, instead of updating global variable NoFramePointerElim in resetTargetOptions, its use in DisableFramePointerElim is replaced with a call to TargetFrameLowering::noFramePointerElim. This function determines on a per-function basis if frame pointer elimination should be disabled. There is no change in functionality except that cl:opt option "disable-fp-elim" can now override function attribute "no-frame-pointer-elim". llvm-svn: 238080
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-2/+2
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-2/+2
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Migrate existing backends that care about software floating pointEric Christopher2015-05-121-0/+1
| | | | | | | | | | | | | | | | | | | | to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
* Refactor: Simplify boolean expressions in ARM targetAlexander Kornienko2015-04-141-1/+1
| | | | | | | | | | Simplify boolean expressions using `true` and `false` with `clang-tidy` http://reviews.llvm.org/D8524 Patch by Richard Thomson! llvm-svn: 234901
* [ARM] Rename v8.1a from "extension" to "architecture"Vladimir Sukharev2015-04-011-1/+1
| | | | | | | | | | | | | | v8.1a is renamed to architecture, following current entity naming approach. Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8767 llvm-svn: 233811
* Remove more superfluous .str() and replace std::string concatenation with Twine.Yaron Keren2015-03-301-1/+1
| | | | | | Following r233392, http://llvm.org/viewvc/llvm-project?rev=233392&view=rev. llvm-svn: 233555
* [AArch64, ARM] Add v8.1a architecture and generic cpuVladimir Sukharev2015-03-261-0/+1
| | | | | | | | | | | | New architecture and cpu added, following http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8505 llvm-svn: 233290
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-2/+2
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-2/+2
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* [ARM] Add support for ARMV6K subtarget (LLVM)Renato Golin2015-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232468
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-2/+2
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-2/+2
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* ARM: Canonicalize access to function attributes, NFCDuncan P. N. Exon Smith2015-02-141-2/+1
| | | | | | | | | | | | Canonicalize access to function attributes to use the simpler API. getAttributes().getAttribute(AttributeSet::FunctionIndex, Kind) => getFnAttribute(Kind) getAttributes().hasAttribute(AttributeSet::FunctionIndex, Kind) => hasFnAttribute(Kind) llvm-svn: 229220
* Remove getSubtargetImpl from ARMISelLowering and cache theEric Christopher2015-01-291-1/+1
| | | | | | | correct subtarget by passing it in during the constructor as TargetLowering is Subtarget specific. llvm-svn: 227401
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-58/+16
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-2/+2
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-181-39/+12
| | | | | | | | | | | | | of the abi we should be using. For targets that don't use the option there's no change, otherwise this allows external users to set the ABI via string and avoid some of the -backend-option pain in clang. Use this option to move the ABI for the ARM port from the Subtarget to the TargetMachine and update the testcases accordingly since it's no longer valid to set via -mattr. llvm-svn: 224492
* Model ARM backend ABI selection after the front end code doing theEric Christopher2014-12-181-18/+34
| | | | | | | | | | | | | | same. This will change the "bare metal" ABI from APCS to AAPCS. The only difference between the front and back end code is that the code for Triple::GNU was added for environment. That will migrate to the front end shortly. Tests updated with the ABI they were originally testing in the case of bare metal (e.g. -mtriple armv7) or with a -gnu for arm-linux triples. llvm-svn: 224489
* ARM: convert isTargetIOS checks to isTargetDarwin.Tim Northover2014-12-111-1/+1
| | | | | | | | | | | The distinction is mostly useful in the front-end. By the time we get here, there are very few situations where we actually want different behaviour for Darwin and IOS (in fact Darwin mostly just exists in a few tests). So this should reduce any surprising weirdness for anyone using it. No functional change on anything anyone actually cares about. llvm-svn: 224035
* Remove redundant calls to isMaterializable.Rafael Espindola2014-11-011-5/+1
| | | | | | | | | | This removes calls to isMaterializable in the following cases: * It was redundant with a call to isDeclaration now that isDeclaration returns the correct answer for materializable functions. * It was followed by a call to Materialize. Just call Materialize and check EC. llvm-svn: 221050
* ARM: drop check for triple that's no longer used.Tim Northover2014-10-151-3/+2
| | | | | | | | | | Early attempts to support AAPCS bare metal MachO targets based the decision on the CPU being compiled for. This was not a particularly great idea and we've got a better option now, but this check remained. No functional change for any target we care about. llvm-svn: 219767
* ARM: remove ARM/Thumb distinction for preferred alignment.Tim Northover2014-10-141-5/+0
| | | | | | | | | | | | Thumb1 has legitimate reasons for preferring 32-bit alignment of types i1/i8/i16, since the 16-bit encoding of "add rD, sp, #imm" requires #imm to be a multiple of 4. However, this is a trade-off betweem code size and RAM usage; the DataLayout string is not the best place to represent it even if desired. So this patch removes the extra Thumb requirements, hopefully making ARM and Thumb completely compatible in this respect. llvm-svn: 219734
* ARM: set preferred aggregate alignment to 32 universally.Tim Northover2014-10-141-4/+3
| | | | | | | | | | | Before, ARM and Thumb mode code had different preferred alignments, which could lead to some rather unexpected results. There's justification for reducing it from the default 64-bits (wasted space), but I don't think there is for going below 32-bits. There's no actual ABI change here, just to reassure people. llvm-svn: 219719
* Use triple's isiOS() and isOSDarwin() methods.Bob Wilson2014-10-091-2/+1
| | | | | | | These methods are already used in lots of places. This makes things more consistent. NFC. llvm-svn: 219386
* Refactor isThumb1Only() && isMClass() into a predicate called isV6M()Renato Golin2014-10-081-5/+4
| | | | | | | | | This must be enforced for all v6M cores, not just the cortex-m0, irregardless of the user-specified alignment. Patch by Charlie Turner. llvm-svn: 219300
* Simplify switch statement in ARM subtarget align accessRenato Golin2014-10-081-30/+24
| | | | | | | | This switch can be reduced to a simpler if/else statement. Patch by Charlie Turner. llvm-svn: 219299
* constify TargetMachine argument.Eric Christopher2014-10-031-1/+1
| | | | llvm-svn: 218930
* We can grab the options struct from the TargetMachine, no need toEric Christopher2014-10-031-2/+2
| | | | | | pass it down in the constructor. llvm-svn: 218929
* | -> ||Richard Trieu2014-09-171-1/+1
| | | | | | No functional change. llvm-svn: 217934
* Remove resetSubtargetFeatures as it is unused.Eric Christopher2014-09-031-18/+2
| | | | llvm-svn: 217071
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-2/+1
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-021-1/+1
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* Rename AtomicExpandLoadLinked into AtomicExpandRobin Morisset2014-08-211-1/+1
| | | | | | | | | | | AtomicExpandLoadLinked is currently rather ARM-specific. This patch is the first of a group that aim at making it more target-independent. See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075873.html for details The command line option is "atomic-expand" llvm-svn: 216231
* Hide two different AlignMode enums in anonymous namespaces. This bug is ↵Alexey Samsonov2014-08-191-0/+2
| | | | | | reported by UBSan. llvm-svn: 216001
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-1/+2
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-2/+1
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the ↵Chris Bieneman2014-07-161-57/+0
| | | | | | TargetRegisterInfo instead of the TargetSubtargetInfo. llvm-svn: 213188
* Added documentation for SizeMultiplier in the ARM subtarget hook for ↵Chris Bieneman2014-07-161-2/+11
| | | | | | | | register coalescing. Also fixed some 80 col violations. No functional code changes. llvm-svn: 213169
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-16/+2
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of ↵Chris Bieneman2014-07-151-0/+51
| | | | | | | | | | coalescing. The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing. This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825. llvm-svn: 213078
* Move function dependent resetting of a subtarget variable out of theEric Christopher2014-07-041-4/+9
| | | | | | | | | | subtarget. This involved having the movt predicate take the current function - since we care about size in instruction selection for whether or not to use movw/movt take the function so we can check the attributes. This required adding the current MachineFunction to FastISel and propagating through. llvm-svn: 212309
* Move all of the ARM subtarget features down onto the subtargetEric Christopher2014-06-261-5/+21
| | | | | | rather than the target machine. llvm-svn: 211799
* Add a new subtarget hook for whether or not we'd like to enableEric Christopher2014-06-191-0/+4
| | | | | | | | | the atomic load linked expander pass to run for a particular subtarget. This requires a check of the subtarget and so save the TargetMachine rather than only TargetLoweringInfo and update all callers. llvm-svn: 211314
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-181-1/+1
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-151-1/+1
| | | | | | back. llvm-svn: 210996
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-131-1/+1
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-131-1/+2
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-131-12/+69
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* Add a subtarget hook: enablePostMachineScheduler.Andrew Trick2014-06-041-0/+7
| | | | | | | | | | | | | | | As requested by AArch64 subtargets. Note that this will have no effect until the AArch64 target actually enables the pass like this: substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); As soon as armv7 switches over, PostMachineScheduler will become the default postRA scheduler, so this won't be necessary any more. Targets using the old postRA schedule would then do: substitutePass(&PostMachineSchedulerID, &PostRASchedulerID); llvm-svn: 210167
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