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* ARM: deduplicate hard-float detection code. NFC.Tim Northover2018-07-181-0/+2
| | | | | | | | ARMSubtarget had a copy/pasted block to determine whether the target was hard-float, but it just delegated to triple features anyway so it's better at the TargetMachine level. llvm-svn: 337384
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-181-5/+0
| | | | | | | | | | | Note: - X86ISelLowering: setLibcallName(SINCOS) was superfluous as InitLibcalls() already does it. - ARMISelLowering: Setting libcallnames for sincos/sincosf seemed superfluous as in the darwin case it wouldn't be used while for all other cases InitLibcalls already does it. llvm-svn: 321036
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* Remove redundant includes from lib/Target/ARM.Michael Zolotukhin2017-12-131-5/+0
| | | | llvm-svn: 320635
* [ARM] Fix incorrect conversion of a tail call to an ordinary callMomchil Velikov2017-11-141-2/+2
| | | | | | | | | | | | | | | | | | | When we emit a tail call for Armv8-M, but then discover that the caller needs to save/restore `LR`, we convert the tail call to an ordinary one, since restoring `LR` takes extra instructions, which may negate the benefits of the tail call. If the callee, however, takes stack arguments, this conversion is incorrect, since nothing has been done to pass the stack arguments. Thus the patch reverts https://reviews.llvm.org/rL294000 Also, we improve the instruction sequence for popping `LR` in the case when we couldn't immediately find a scratch low register, but we can use as a temporary one of the callee-saved low registers and restore `LR` before popping other callee-saves. Differential Revision: https://reviews.llvm.org/D39599 llvm-svn: 318143
* [arm] Fix Unnecessary reloads from GOT.Evgeniy Stepanov2017-11-131-5/+3
| | | | | | | | | | | | Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
* [ARM] Fix SJLJ exception handling when manually chosen on a platform where ↵Martin Storsjo2017-09-281-1/+3
| | | | | | | | it isn't default Differential Revision: https://reviews.llvm.org/D38252 llvm-svn: 314450
* [ARM] Reverse PostRASched subtarget feature logicSam Parker2017-08-311-8/+3
| | | | | | | | | | | | Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 llvm-svn: 312226
* [ARM] GlobalISel: Select globals in PIC modeDiana Picus2017-08-291-0/+7
| | | | | | | | | | | | | | Support the selection of G_GLOBAL_VALUE in the PIC relocation model. For simplicity we use the same pseudoinstructions for both Darwin and ELF: (MOV|LDRLIT)_ga_pcrel(_ldr). This is new for ELF, so it requires a small update to the ARM pseudo expansion pass to make sure it adds the correct constant pool modifier and add-current-address in the case of ELF. Differential Revision: https://reviews.llvm.org/D36507 llvm-svn: 311992
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-0/+2
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* [ARM] Add PostRAScheduler optionSam Parker2017-08-181-0/+4
| | | | | | | | | | | This patch adds the option to allow also using the PostRA scheduler, which brings the ARM backend inline with AArch64 targets. The SchedModel can also set 'PostRAScheduler', as the R52 does, so also query this property in the overridden function. Differential Revision: https://reviews.llvm.org/D36866 llvm-svn: 311162
* Reapply "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-151-42/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit r310425, thus reapplying r310335 with a fix for link issue of the AArch64 unittests on Linux bots when BUILD_SHARED_LIBS is ON. Original commit message: [GlobalISel] Remove the GISelAccessor API. Its sole purpose was to avoid spreading around ifdefs related to building global-isel. Since r309990, GlobalISel is not optional anymore, thus, we can get rid of this mechanism all together. NFC. ---- The fix for the link issue consists in adding the GlobalISel library in the list of dependencies for the AArch64 unittests. This dependency comes from the use of AArch64Subtarget that needs to know how to destruct the GISel related APIs when being detroyed. Thanks to Bill Seurer and Ahmed Bougacha for helping me reproducing and understand the problem. llvm-svn: 310969
* [ARM] Emit error when ARM exec mode is not available.Florian Hahn2017-08-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A similar error message has been removed from the ARMTargetMachineBase constructor in r306939. With this patch, we generate an error message for the example below, compiled with -mcpu=cortex-m0, which does not have ARM execution mode. __attribute__((target("arm"))) int foo(int a, int b) { return a + b % a; } __attribute__((target("thumb"))) int bar(int a, int b) { return a + b % a; } By adding this error message to ARMBaseTargetMachine::getSubtargetImpl, we can deal with functions that set -thumb-mode in target-features. At the moment it seems like Clang does not have access to target-feature specific information, so adding the error message to the frontend will be harder. Reviewers: echristo, richard.barton.arm, t.p.northover, rengolin, efriedma Reviewed By: echristo, efriedma Subscribers: efriedma, aemerson, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D35627 llvm-svn: 310486
* Revert "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-081-8/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit r310115. It causes a linker failure for the one of the unittests of AArch64 on one of the linux bot: http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/3429 : && /home/fedora/gcc/install/gcc-7.1.0/bin/g++ -fPIC -fvisibility-inlines-hidden -Werror=date-time -std=c++11 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wno-maybe-uninitialized -Wdelete-non-virtual-dtor -Wno-comment -ffunction-sections -fdata-sections -O2 -L/home/fedora/gcc/install/gcc-7.1.0/lib64 -Wl,-allow-shlib-undefined -Wl,-O3 -Wl,--gc-sections unittests/Target/AArch64/CMakeFiles/AArch64Tests.dir/InstSizes.cpp.o -o unittests/Target/AArch64/AArch64Tests lib/libLLVMAArch64CodeGen.so.6.0.0svn lib/libLLVMAArch64Desc.so.6.0.0svn lib/libLLVMAArch64Info.so.6.0.0svn lib/libLLVMCodeGen.so.6.0.0svn lib/libLLVMCore.so.6.0.0svn lib/libLLVMMC.so.6.0.0svn lib/libLLVMMIRParser.so.6.0.0svn lib/libLLVMSelectionDAG.so.6.0.0svn lib/libLLVMTarget.so.6.0.0svn lib/libLLVMSupport.so.6.0.0svn -lpthread lib/libgtest_main.so.6.0.0svn lib/libgtest.so.6.0.0svn -lpthread -Wl,-rpath,/home/buildbots/ppc64le-clang-multistage-test/clang-ppc64le-multistage/stage1/lib && : unittests/Target/AArch64/CMakeFiles/AArch64Tests.dir/InstSizes.cpp.o:(.toc+0x0): undefined reference to `vtable for llvm::LegalizerInfo' unittests/Target/AArch64/CMakeFiles/AArch64Tests.dir/InstSizes.cpp.o:(.toc+0x8): undefined reference to `vtable for llvm::RegisterBankInfo' The particularity of this bot is that it is built with BUILD_SHARED_LIBS=ON However, I was not able to reproduce the problem so far. Reverting to unblock the bot. llvm-svn: 310425
* [GlobalISel] Remove the GISelAccessor API.Quentin Colombet2017-08-041-42/+8
| | | | | | | | | | Its sole purpose was to avoid spreading around ifdefs related to building global-isel. Since r309990, GlobalISel is not optional anymore, thus, we can get rid of this mechanism all together. NFC. llvm-svn: 310115
* [GlobalISel] Make GlobalISel a non-optional library.Quentin Colombet2017-08-031-10/+0
| | | | | | | | With this change, the GlobalISel library gets always built. In particular, this is not possible to opt GlobalISel out of the build using the LLVM_BUILD_GLOBAL_ISEL variable any more. llvm-svn: 309990
* [ARM] Add use-misched feature, to enable the MachineScheduler.Florian Hahn2017-07-271-7/+6
| | | | | | | | | | | | | | | | | | | Summary: This change makes it easier to experiment with the MachineScheduler in the ARM backend and also makes it very explicit which CPUs use the MachineScheduler (currently only swift and cyclone). Reviewers: MatzeB, t.p.northover, javed.absar Reviewed By: MatzeB Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35935 llvm-svn: 309316
* [TargetParser] Use enum classes for various ARM kind enums.Florian Hahn2017-07-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Using c++11 enum classes ensures that only valid enum values are used for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the need for checks that the provided values map to a proper enum value, allows us to get rid of AK_LAST and prevents comparing values from different enums. It also removes a bunch of static_cast from unsigned to enum values and vice versa, at the cost of introducing static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind. FPUKind and ArchExtKind are the only remaining old-style enum in TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style enum, but FPUKind can be converted too, but this patch is quite big, so could do this in a follow-up patch. I could also split this patch up a bit, if people would prefer that. Reviewers: rengolin, javed.absar, chandlerc, rovka Reviewed By: rovka Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35882 llvm-svn: 309287
* [ARM] Minor cosmetic edits (NFC)Evandro Menezes2017-07-261-1/+1
| | | | | | Change the order of a case and the description for Exynos Mx processors. llvm-svn: 309184
* Remove the default ARMSubtarget from the ARM TargetMachine.Eric Christopher2017-07-011-0/+3
| | | | | | | This enables us to ensure better LTO and code generation in the face of module linking. Remove a report_fatal_error from the TargetMachine and replace it with an assert in ARMSubtarget - and remove the test that depended on the error. The assertion will still fire in the case that we were reporting before, but error reporting needs to be in front end tools if possible for options parsing. llvm-svn: 306939
* Rewrite ARM execute only support to avoid the use of a command line flag and ↵Eric Christopher2017-07-011-8/+2
| | | | | | | | unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
* [ARM] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-07-011-1/+63
| | | | | | NFC llvm-svn: 306920
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* Revert "Revert "[ARM] Add Kryo to available targets""Yi Kong2017-04-061-0/+1
| | | | | | | | This reverts commit dc9458d5a747a02a9a8f198b84c2b92a6939a8dd. Added missing case for PreISelOperandLatencyAdjustment. llvm-svn: 299724
* [ARM] Change TCReturn to tBL if tailcall optimization fails.Sanne Wouda2017-02-031-6/+6
| | | | | | | | | | | | | | | | | | Summary: The tail call optimisation is performed before register allocation, so at that point we don't know if LR is being spilt or not. If LR was spilt to the stack, then we cannot do a tail call optimisation. That would involve popping back into LR which is not possible in Thumb1 code. Reviewers: rengolin, jmolloy, rovka, olista01 Reviewed By: olista01 Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D29020 llvm-svn: 294000
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-271-11/+13
| | | | | | minor fixes (NFC). llvm-svn: 293348
* Fix for build warning in execute-only supportPrakhar Bahuguna2016-12-151-2/+2
| | | | llvm-svn: 289788
* [ARM] Implement execute-only support in CodeGenPrakhar Bahuguna2016-12-151-2/+12
| | | | | | | | | | | | | | | | | | | | This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
* [ARM] Add plumbing for GlobalISelDiana Picus2016-11-111-1/+21
| | | | | | Add GlobalISel skeleton, up to the point where we can select a ret void. llvm-svn: 286573
* [Cortex-M0] Atomic loweringWeiming Zhao2016-11-031-3/+1
| | | | | | | | | | | | Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* [ARM]: add missing switch case for cortex-r52Javed Absar2016-10-071-0/+1
| | | | | | | Adds a missing switch case for handling cortex-r52 in init-subtarget-features. llvm-svn: 283551
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-191-0/+5
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* Revert "[XRay] ARM 32-bit no-Thumb support in LLVM"Renato Golin2016-09-081-5/+0
| | | | | | | | | | And associated commits, as they broke the Thumb bots. This reverts commit r280935. This reverts commit r280891. This reverts commit r280888. llvm-svn: 280967
* [ARM XRay] Try to fix Thumb-only failureRenato Golin2016-09-081-1/+1
| | | | | | | I mised the check that it had to support ARM to work. This commit tries to fix that, to make sure we don't emit ARM code in Thumb-only mode. llvm-svn: 280935
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-081-0/+5
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: 1. https://reviews.llvm.org/D23932 (Clang test) 2. https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 280888
* Use isTargetMachO instead of isTargetDarwin.Rafael Espindola2016-08-241-1/+1
| | | | llvm-svn: 279655
* Some places that could using TargetParser in LLVM. NFC.Zijiao Ma2016-08-171-2/+4
| | | | llvm-svn: 278888
* [ARM] Add support for embedded position-independent codeOliver Stannard2016-08-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for some new relocation models to the ARM backend: * Read-only position independence (ROPI): Code and read-only data is accessed PC-relative. The offsets between all code and RO data sections are known at static link time. This does not affect read-write data. * Read-write position independence (RWPI): Read-write data is accessed relative to the static base register (r9). The offsets between all writeable data sections are known at static link time. This does not affect read-only data. These two modes are independent (they specify how different objects should be addressed), so they can be used individually or together. They are otherwise the same as the "static" relocation model, and are not compatible with SysV-style PIC using a global offset table. These modes are normally used by bare-metal systems or systems with small real-time operating systems. They are designed to avoid the need for a dynamic linker, the only initialisation required is setting r9 to an appropriate value for RWPI code. I have only added support to SelectionDAG, not FastISel, because FastISel is currently disabled for bare-metal targets where these modes would be used. Differential Revision: https://reviews.llvm.org/D23195 llvm-svn: 278015
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-061-0/+2
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* Delete unused includes. NFC.Rafael Espindola2016-06-301-1/+0
| | | | llvm-svn: 274225
* Don't pass a Reloc::Model to GVIsIndirectSymbol.Rafael Espindola2016-06-281-5/+2
| | | | | | | | It already has access to it. While at it, rename it to isGVIndirectSymbol. llvm-svn: 274023
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-271-1/+1
| | | | | | Should fix the shared library build. llvm-svn: 273958
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-271-28/+3
| | | | | | | | Same as r273556, but with C++11 member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273873
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 2). NFCIDiana Picus2016-06-271-3/+51
| | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21685 llvm-svn: 273853
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-231-66/+22
| | | | | | | | | Move most of the initializations in ARMSubtarget::initializeEnvironment to member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273556
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-231-0/+6
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-031-1/+2
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* Start using shouldAssumeDSOLocal on ARM.Rafael Espindola2016-05-271-29/+9
| | | | | | Given where this is used it should be a nop. llvm-svn: 271066
* ARMv7k: base ABI decision on v7k Arch rather than watchos OS.Tim Northover2016-01-271-2/+2
| | | | | | | | Various bits we want to use the new ABI actually compile with "-arch armv7k -miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how slices work. llvm-svn: 258975
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