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* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-11/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-2/+2
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-8/+8
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* use simplified operand addition methods.Chris Lattner2007-12-301-8/+9
| | | | llvm-svn: 45437
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* DohEvan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44694
* Fix a compilation warning.Evan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44692
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-7/+41
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-021-1/+5
| | | | llvm-svn: 44517
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-131-1/+1
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-1/+4
| | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-0/+5
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-181-2/+2
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng2007-10-181-4/+4
| | | | | | public interface. llvm-svn: 43150
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-051-21/+110
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-261-4/+10
| | | | | | Tested with "make check"! llvm-svn: 42346
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-2/+2
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Only adjust esp around calls in presence of alloca.Evan Cheng2007-07-191-1/+1
| | | | llvm-svn: 40030
* Long live the exception handling!Anton Korobeynikov2007-07-141-2/+3
| | | | | | | | | | | | | | | This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-5/+9
| | | | | | the 's' bit. llvm-svn: 38501
* Added ARM::CPSR to represent ARM CPSR status register.Evan Cheng2007-07-051-49/+59
| | | | llvm-svn: 37894
* Add missing const qualifiers.Evan Cheng2007-05-291-3/+3
| | | | llvm-svn: 37342
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-48/+77
| | | | llvm-svn: 37066
* Fix PR1390 in a better way.Lauro Ramos Venancio2007-05-071-12/+41
| | | | llvm-svn: 36916
* Fix PR1390.Lauro Ramos Venancio2007-05-051-38/+10
| | | | | | Don't spill extra register to align the stack. llvm-svn: 36814
* Debug support for arm-linux.Lauro Ramos Venancio2007-05-031-0/+5
| | | | | | Patch by Raul Herbster. llvm-svn: 36690
* eliminateFrameIndex() change.Evan Cheng2007-05-011-3/+4
| | | | llvm-svn: 36626
* Under normal circumstances, when a frame pointer is not required, we reserveEvan Cheng2007-05-011-3/+27
| | | | | | | | | | | | argument space for call sites in the function immediately on entry to the current function. This eliminates the need for add/sub sp brackets around call sites. However, this is not always a good idea. If the "call frame" is large and the target load / store instructions have small immediate field to encode sp offset, this can cause poor codegen. In the worst case, this can make it impossible to scavenge a register if the reserved spill slot is pushed too far apart from sp / fp. llvm-svn: 36607
* add parenthesis.Lauro Ramos Venancio2007-04-271-2/+2
| | | | llvm-svn: 36514
* In Thumb mode, the frame register must be R7.Lauro Ramos Venancio2007-04-271-2/+2
| | | | llvm-svn: 36512
* Match MachineFunction::UsedPhysRegs changes.Evan Cheng2007-04-251-9/+6
| | | | llvm-svn: 36452
* Fix a bug in getFrameRegister.Lauro Ramos Venancio2007-04-191-1/+4
| | | | | | Reported by Raul Herbster. llvm-svn: 36262
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-161-1/+1
| | | | | | target for tabs checking. llvm-svn: 36146
* Fixed a bug that causes codegen of noop like add r0, r0, #0.Evan Cheng2007-04-031-1/+1
| | | | llvm-svn: 35627
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-201-16/+35
| | | | llvm-svn: 35205
* Fix naming inconsistencies.Evan Cheng2007-03-191-17/+17
| | | | llvm-svn: 35163
* Fix one more Thumb eliminateFrameIndex bug.Evan Cheng2007-03-071-9/+23
| | | | llvm-svn: 34990
* Register scavenging is now on by default for ARM.Evan Cheng2007-03-061-3/+4
| | | | llvm-svn: 34987
* Scavenge a register using the register scavenger when needed.Evan Cheng2007-03-061-8/+107
| | | | llvm-svn: 34966
* eliminate unnecessary reset of SP in epilog on darwinDale Johannesen2007-03-021-1/+1
| | | | llvm-svn: 34824
* Use a spilled free callee-saved register as scratch register.Evan Cheng2007-03-011-3/+17
| | | | llvm-svn: 34785
* - Track which callee-saved registers are spilled.Evan Cheng2007-03-011-10/+18
| | | | | | - Some code clean up. llvm-svn: 34783
* Doh. ARM::PC is obvious a reserved register.Evan Cheng2007-02-281-0/+1
| | | | llvm-svn: 34763
* Make requiresRegisterScavenging determination on a per MachineFunction basis.Evan Cheng2007-02-281-2/+4
| | | | llvm-svn: 34711
* Start making use of RegScavenger.Evan Cheng2007-02-281-8/+12
| | | | llvm-svn: 34708
* Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve ↵Evan Cheng2007-02-271-27/+43
| | | | | | register kill info. llvm-svn: 34692
* bugfix: SP wasn't updated for varargs when frame pointer was eliminated.Lauro Ramos Venancio2007-02-231-63/+63
| | | | llvm-svn: 34537
* Add option to turn on register scavenger; By default, spills kills the ↵Evan Cheng2007-02-231-6/+18
| | | | | | register being stored. llvm-svn: 34514
* Support to provide exception and selector registers.Jim Laskey2007-02-211-0/+10
| | | | llvm-svn: 34482
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