summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMPerfectShuffle.h
Commit message (Collapse)AuthorAgeFilesLines
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-0/+5
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner2011-05-181-1342/+1341
| | | | | | | | splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. llvm-svn: 131529
* vrev is incorrectly defined in the perfect shuffle table. The ordering is ↵Tanya Lattner2011-05-171-6565/+6566
| | | | | | backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. llvm-svn: 131488
* Regenerate. No functional change, just cleanup.Jim Grosbach2010-10-141-6561/+6561
| | | | llvm-svn: 116459
* RegenerateAnton Korobeynikov2009-09-251-4272/+4272
| | | | llvm-svn: 82814
* Add lowering of ARM 4-element shuffles to multiple instructios via ↵Anton Korobeynikov2009-08-211-0/+6586
perfectshuffle-generated table. llvm-svn: 79624
OpenPOWER on IntegriCloud