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path: root/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
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* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Re-apply r214881: Fix return sequence on armv4 thumbJonathan Roelofs2014-08-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts r214893, re-applying r214881 with the test case relaxed a bit to satiate the build bots. POP on armv4t cannot be used to change thumb state (unilke later non-m-class architectures), therefore we need a different return sequence that uses 'bx' instead: POP {r3} ADD sp, #offset BX r3 This patch also fixes an issue where the return value in r3 would get clobbered for functions that return 128 bits of data. In that case, we generate this sequence instead: MOV ip, r3 POP {r3} ADD sp, #offset MOV lr, r3 MOV r3, ip BX lr http://reviews.llvm.org/D4748 llvm-svn: 214928
* Revert r214881 because it broke lots of build-botsJonathan Roelofs2014-08-051-8/+1
| | | | llvm-svn: 214893
* Fix return sequence on armv4 thumbJonathan Roelofs2014-08-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | POP on armv4t cannot be used to change thumb state (unilke later non-m-class architectures), therefore we need a different return sequence that uses 'bx' instead: POP {r3} ADD sp, #offset BX r3 This patch also fixes an issue where the return value in r3 would get clobbered for functions that return 128 bits of data. In that case, we generate this sequence instead: MOV ip, r3 POP {r3} ADD sp, #offset MOV lr, r3 MOV r3, ip BX lr http://reviews.llvm.org/D4748 llvm-svn: 214881
* [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of ↵Chris Bieneman2014-07-151-0/+14
| | | | | | | | | | coalescing. The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing. This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825. llvm-svn: 213078
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-181-10/+1
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-181-1/+1
| | | | llvm-svn: 211141
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-151-1/+10
| | | | | | back. llvm-svn: 210996
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-131-10/+1
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* ARM: Add support for segmented stacksOliver Stannard2014-04-021-0/+7
| | | | | | Patch by Alex Crichton, ILyoan, Luqman Aden and Svetoslav. llvm-svn: 205430
* Use 16 byte stack alignment for NaCl on ARMMark Seaborn2014-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's ARM ABI uses 16 byte stack alignment, so set that in ARMSubtarget.cpp. Using 16 byte alignment exposes an issue in code generation in which a varargs function leaves a 4 byte gap between the values of r1-r3 saved to the stack and the following arguments that were passed on the stack. (Previously, this code only needed to support 4 byte and 8 byte alignment.) With this issue, llc generated: varargs_func: sub sp, sp, #16 push {lr} sub sp, sp, #12 add r0, sp, #16 // Should be 20 stm r0, {r1, r2, r3} ldr r0, .LCPI0_0 // Address of va_list add r1, sp, #16 str r1, [r0] bl external_func Fix the bug by checking for "Align > 4". Also simplify the code by using OffsetToAlignment(), and update comments. Differential Revision: http://llvm-reviews.chandlerc.com/D2677 llvm-svn: 201497
* ARM: remove unnecessary state-tracking during frame lowering.Tim Northover2013-11-041-61/+0
| | | | | | | | | | | | | | | | | | | | | ResolveFrameIndex had what appeared to be a very nasty hack for when the frame-index referred to a callee-saved register. In this case it "adjusted" the offset so that the address was correct if (and only if) the MachineInstr immediately followed the respective push. This "worked" for all forms of GPR & DPR but was only ever used to set the frame pointer itself, and once this was put in a more sensible location the entire state-tracking machinery it relied on became redundant. So I stripped it. The only wrinkle is that "add r7, sp, #0" might theoretically be slower (need an actual ALU slot) compared to "mov r7, sp" so I added a micro-optimisation that also makes emitARMRegUpdate and emitT2RegUpdate also work when NumBytes == 0. No test changes since there shouldn't be any functionality change. llvm-svn: 194025
* PR15868 fix.Stepan Dyatkovskiy2013-05-201-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N*8: we add padding to GPRs part, so part's last byte must be recovered at address K*8-1. We need to do it, since remained (stack) part of parameter starts from address K*8, and we need to "attach" "GPRs head" without gaps to it: Stack: |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct *all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. llvm-svn: 182237
* Refactoring patch.Stepan Dyatkovskiy2013-04-301-5/+5
| | | | | | | | | | | | 1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong. This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method. 2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed. 3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons. llvm-svn: 180774
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-2/+2
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-2/+10
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-231-0/+16
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+1
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-141-17/+0
| | | | llvm-svn: 125534
* Save a mapping between original and cloned constpool entries.Anton Korobeynikov2011-01-301-0/+17
| | | | llvm-svn: 124570
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-11/+11
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Fix a comment.Bob Wilson2011-01-151-2/+2
| | | | llvm-svn: 123497
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-26/+53
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. llvm-svn: 118026
* Update comments to remove obsolete references.Jim Grosbach2010-10-191-6/+5
| | | | llvm-svn: 116863
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-201-51/+25
| | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-101-2/+9
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-9/+2
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-2/+9
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-2/+10
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-2/+8
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* eliminate the ARMFunctionInfo::Align member, using Chris Lattner2010-01-271-10/+0
| | | | | | MachineFunction::Alignment instead. llvm-svn: 94701
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-10/+2
| | | | llvm-svn: 83522
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-3/+3
| | | | llvm-svn: 78666
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75067
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-1/+9
| | | | llvm-svn: 74543
* Add explicit keywords.Dan Gohman2009-06-051-1/+1
| | | | llvm-svn: 72969
* Use ARMFunctionInfo to track number of constpool entries and jumptables.Evan Cheng2008-11-081-3/+21
| | | | llvm-svn: 58877
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* add Align field, and use when generating function alignmentDale Johannesen2007-04-231-2/+12
| | | | llvm-svn: 36371
* - Track which callee-saved registers are spilled.Evan Cheng2007-03-011-9/+28
| | | | | | - Some code clean up. llvm-svn: 34783
* Switch from std::vector<bool> to BitVector.Evan Cheng2007-03-011-12/+32
| | | | llvm-svn: 34781
* In thumb mode, R3 is reserved, but it can be live in to the function. IfEvan Cheng2007-02-071-2/+11
| | | | | | | | that is the case, whenever we use it as a scratch register, save it to R12 first and then restore it after the use. This is a temporary and truly horrible workaround! llvm-svn: 33999
* - In thumb mode, if size of MachineFunction is >= 2048, force LR to beEvan Cheng2007-01-301-7/+7
| | | | | | | | | | | | | spilled (if it is not already). - If LR is spilled, use BL to implement far jumps. LR is not used as a GPR in thumb mode so it can be clobbered if it is properly spilled / restored in prologue / epilogue. - If LR is force spilled but no far jump has been emitted, try undo'ing the spill by: push lr -> delete pop pc -> bx lr llvm-svn: 33650
* Remember if LR register has been spilled in this function.Evan Cheng2007-01-291-4/+12
| | | | llvm-svn: 33632
* Getting rid uses of evil std::set<>Evan Cheng2007-01-251-15/+33
| | | | llvm-svn: 33496
* Clean up ARM PEI code.Evan Cheng2007-01-201-7/+7
| | | | llvm-svn: 33389
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+136
llvm-svn: 33353
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