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path: root/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
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* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-231-0/+16
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+1
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-141-17/+0
| | | | llvm-svn: 125534
* Save a mapping between original and cloned constpool entries.Anton Korobeynikov2011-01-301-0/+17
| | | | llvm-svn: 124570
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-11/+11
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Fix a comment.Bob Wilson2011-01-151-2/+2
| | | | llvm-svn: 123497
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-26/+53
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. llvm-svn: 118026
* Update comments to remove obsolete references.Jim Grosbach2010-10-191-6/+5
| | | | llvm-svn: 116863
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-201-51/+25
| | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-101-2/+9
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-9/+2
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-2/+9
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-2/+10
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-2/+8
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* eliminate the ARMFunctionInfo::Align member, using Chris Lattner2010-01-271-10/+0
| | | | | | MachineFunction::Alignment instead. llvm-svn: 94701
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-10/+2
| | | | llvm-svn: 83522
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-3/+3
| | | | llvm-svn: 78666
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75067
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-1/+9
| | | | llvm-svn: 74543
* Add explicit keywords.Dan Gohman2009-06-051-1/+1
| | | | llvm-svn: 72969
* Use ARMFunctionInfo to track number of constpool entries and jumptables.Evan Cheng2008-11-081-3/+21
| | | | llvm-svn: 58877
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* add Align field, and use when generating function alignmentDale Johannesen2007-04-231-2/+12
| | | | llvm-svn: 36371
* - Track which callee-saved registers are spilled.Evan Cheng2007-03-011-9/+28
| | | | | | - Some code clean up. llvm-svn: 34783
* Switch from std::vector<bool> to BitVector.Evan Cheng2007-03-011-12/+32
| | | | llvm-svn: 34781
* In thumb mode, R3 is reserved, but it can be live in to the function. IfEvan Cheng2007-02-071-2/+11
| | | | | | | | that is the case, whenever we use it as a scratch register, save it to R12 first and then restore it after the use. This is a temporary and truly horrible workaround! llvm-svn: 33999
* - In thumb mode, if size of MachineFunction is >= 2048, force LR to beEvan Cheng2007-01-301-7/+7
| | | | | | | | | | | | | spilled (if it is not already). - If LR is spilled, use BL to implement far jumps. LR is not used as a GPR in thumb mode so it can be clobbered if it is properly spilled / restored in prologue / epilogue. - If LR is force spilled but no far jump has been emitted, try undo'ing the spill by: push lr -> delete pop pc -> bx lr llvm-svn: 33650
* Remember if LR register has been spilled in this function.Evan Cheng2007-01-291-4/+12
| | | | llvm-svn: 33632
* Getting rid uses of evil std::set<>Evan Cheng2007-01-251-15/+33
| | | | llvm-svn: 33496
* Clean up ARM PEI code.Evan Cheng2007-01-201-7/+7
| | | | llvm-svn: 33389
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+136
llvm-svn: 33353
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