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path: root/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-301-15/+0
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Fix handling of ARM negative pc-relative fixups for loads and stores.Jim Grosbach2010-11-301-4/+9
| | | | llvm-svn: 120480
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-301-0/+18
| | | | llvm-svn: 120449
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-301-0/+24
| | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-301-2/+24
| | | | llvm-svn: 120364
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+28
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
* Provide Thumb2 encodings for basic loads and stores.Owen Anderson2010-11-291-0/+55
| | | | llvm-svn: 120340
* Fix a compiler warning about Kind being used uninitializedDuncan Sands2010-11-221-1/+1
| | | | | | when assertions are disabled. llvm-svn: 119962
* Minor cleanups to a few llvm_unreachable() calls.Jim Grosbach2010-11-191-6/+3
| | | | llvm-svn: 119767
* An 'unreachable' shouldn't have a '0 &&' prefix.Bill Wendling2010-11-191-2/+2
| | | | llvm-svn: 119762
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+31
| | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
* Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling2010-11-171-5/+26
| | | | | | | "getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. llvm-svn: 119435
* ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach2010-11-151-16/+61
| | | | llvm-svn: 119180
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-1/+1
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-121-0/+52
| | | | llvm-svn: 118924
* Start of support for binary emit of 16-it Thumb instructions.Jim Grosbach2010-11-111-3/+10
| | | | llvm-svn: 118859
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-111-0/+17
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-111-1/+18
| | | | llvm-svn: 118843
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-111-0/+23
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-111-3/+28
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-111-0/+23
| | | | llvm-svn: 118794
* ARM STRH encoding information.Jim Grosbach2010-11-111-1/+26
| | | | llvm-svn: 118757
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-101-0/+13
| | | | llvm-svn: 118736
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. llvm-svn: 118587
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-091-0/+45
| | | | llvm-svn: 118513
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-091-8/+2
| | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. llvm-svn: 118469
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-091-5/+8
| | | | llvm-svn: 118462
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | llvm-svn: 118458
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-041-30/+51
| | | | | | | tweaking when we start using it for object file emission or JIT, but it's a start. llvm-svn: 118221
* Teach ARM Target to use the tblgen support for generating an MC'izedJim Grosbach2010-11-031-46/+62
| | | | | | CodeEmitter. llvm-svn: 118209
* trailing whitespaceJim Grosbach2010-11-031-2/+2
| | | | llvm-svn: 118199
* Put the PC encoding in the correct bit position.Bill Wendling2010-11-031-1/+1
| | | | llvm-svn: 118151
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-19/+65
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Obsessive formatting changes. No functionality impact.Bill Wendling2010-11-021-31/+37
| | | | llvm-svn: 118103
* Omit unused parameter name.Bill Wendling2010-11-021-1/+1
| | | | llvm-svn: 118099
* Simplify the EncodeInstruction method now that a lot of the special case stuffBill Wendling2010-11-021-13/+6
| | | | | | is handled with the MC encoder. llvm-svn: 118098
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-21/+20
| | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
* Rename encoder methods to match naming convention.Owen Anderson2010-11-021-4/+4
| | | | llvm-svn: 118093
* Add correct encodings for the rest of the vld instructions that we generate.Owen Anderson2010-11-021-1/+1
| | | | llvm-svn: 118053
* Add correct NEON encodings for vld2, vld3, and vld4 basic variants.Owen Anderson2010-11-021-0/+9
| | | | llvm-svn: 117997
* Add aesthetic break.Owen Anderson2010-11-021-1/+1
| | | | llvm-svn: 117986
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-021-1/+17
| | | | llvm-svn: 117984
* Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXMEJim Grosbach2010-11-011-1/+10
| | | | | | for handling the fixup necessary. llvm-svn: 117978
* Remove unused function.Jim Grosbach2010-11-011-13/+0
| | | | llvm-svn: 117977
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117766
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-301-0/+15
| | | | llvm-svn: 117753
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-291-1/+1
| | | | | | encoder functions. llvm-svn: 117738
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-3/+9
| | | | llvm-svn: 117571
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+4
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
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