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* Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*Cameron Zwarich2011-05-171-1/+1
| | | | | | take r13, so we can just make it a GPR. This fixes PR8825. llvm-svn: 131507
* Correct a minor problem with the Thumb2 LDREX and STREX instruction ↵Cameron Zwarich2011-05-171-1/+1
| | | | | | | | encodings. They were marked as taking a tGPR when in reality they take an rGPR. llvm-svn: 131506
* Mark ultra-super-registers QQQQ as call-clobbered instead of the D ↵Jakob Stoklund Olesen2011-05-031-4/+3
| | | | | | | | | | | | | | | sub-registers. LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites Q0, so if Q0 is live-in to a function, its live range will extend beyond a function call that only clobbers D0 and D1. This shows up in the ARM/2009-11-01-NeonMoves test case. LiveVariables should probably implement the much stricter rules for physreg liveness that RAFast imposes - a physreg is killed by the first use of any alias. llvm-svn: 130801
* Fold ARM coprocessor intrinsics patterns into the instructions defs wheneverBruno Cardoso Lopes2011-05-031-21/+15
| | | | | | it's possible. llvm-svn: 130764
* Add a few ARM coprocessor intrinsics. Testcases includedBruno Cardoso Lopes2011-05-031-0/+16
| | | | llvm-svn: 130763
* Switch to ImmLeaf (which can be used by FastISel) for a few more common ↵Eli Friedman2011-04-291-1/+3
| | | | | | ARM/Thumb2 patterns. llvm-svn: 130552
* Teach Thumb2 isel to fold and->rotr ==> ROR.Andrew Trick2011-04-291-0/+9
| | | | | | Generalization of Nate Begeman's patch! llvm-svn: 130502
* Let the immediate leaf pattern take transforms and switch the signedEric Christopher2011-04-281-4/+4
| | | | | | | | immediate patterns in arm to using the pattern. Handles rdar://9299434 llvm-svn: 130386
* Thumb2 and ARM add/subtract with carry fixes.Andrew Trick2011-04-231-42/+23
| | | | | | | | | | | | | Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+2
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* For t2BFI, both Inst{26} and Inst{5} "should" be 0.Johnny Chen2011-04-151-0/+4
| | | | | Ref: I.1 Instruction encoding diagrams and pseudocode llvm-svn: 129552
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-2/+2
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Forgot to add this change for ↵Johnny Chen2011-04-131-4/+4
| | | | | | http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. llvm-svn: 129451
* Add @earlyclobber constraints to the writeback register of all ARM store ↵Jakob Stoklund Olesen2011-04-121-6/+12
| | | | | | | | | | instructions. The ARMARM specifies these instructions as unpredictable when storing the writeback register. This shouldn't affect code generation much since storing a pointer to itself is quite rare. llvm-svn: 129409
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-4/+5
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-0/+3
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-29/+38
| | | | llvm-svn: 128236
* Change MRC and MRC2 instructions to model the output register properlyBruno Cardoso Lopes2011-03-221-6/+8
| | | | llvm-svn: 128085
* Match a few more obvious patterns to revsh. rdar://9147637.Evan Cheng2011-03-181-1/+7
| | | | llvm-svn: 127913
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-181-1/+7
| | | | llvm-svn: 127888
* Remove some dead patterns.Jim Grosbach2011-03-141-34/+0
| | | | llvm-svn: 127601
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-15/+14
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-31/+30
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-2/+17
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Remove inaccurate comments: so_imm and t2_so_imm operands are not encodedBob Wilson2011-02-071-4/+1
| | | | | | until the instructions are emitted or printed. llvm-svn: 125010
* fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructionsBruno Cardoso Lopes2011-01-261-0/+1
| | | | llvm-svn: 124288
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-6/+12
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes2011-01-211-7/+12
| | | | | | | qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
* Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes2011-01-201-4/+7
| | | | llvm-svn: 123936
* Change instruction names for consistencyBruno Cardoso Lopes2011-01-201-4/+6
| | | | llvm-svn: 123930
* Add cdp/cdp2 instructions for thumb/thumb2Bruno Cardoso Lopes2011-01-201-0/+25
| | | | llvm-svn: 123929
* Add mcr*2 and mr*c2 support to thumb2 targetsBruno Cardoso Lopes2011-01-201-0/+56
| | | | llvm-svn: 123919
* Correct itinerary entry for t2MOV_pic_ga_add_pc.Evan Cheng2011-01-201-1/+1
| | | | llvm-svn: 123907
* Sorry, several patches in one.Evan Cheng2011-01-201-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Don't forget to emit the load from indirect symbol when using movw + movt to ↵Evan Cheng2011-01-191-2/+3
| | | | | | materialize GA indirect symbols. llvm-svn: 123809
* Fix MRS encoding for arm and thumb.Bruno Cardoso Lopes2011-01-181-0/+1
| | | | llvm-svn: 123778
* Fix the encoding of t2ISB by using the right class and also parse it correctlyBruno Cardoso Lopes2011-01-181-1/+1
| | | | llvm-svn: 123776
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-13/+32
| | | | | | instruction llvm-svn: 123770
* McARM: Start marking T2 address operands as such, for the benefit of the parser.Daniel Dunbar2011-01-181-0/+5
| | | | llvm-svn: 123722
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-2/+15
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-3/+4
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* McARM: Mark some T2 ...s instructions as codegen only, they aren't realDaniel Dunbar2011-01-101-4/+4
| | | | | | instructions but are restricted pseudo forms. llvm-svn: 123177
* Add bits 31-28 to the Thumb2 encoding of TBB/TBH.Jim Grosbach2010-12-171-2/+2
| | | | llvm-svn: 122076
* Tweak a few pseudo-inst pattern base classes.Jim Grosbach2010-12-151-4/+4
| | | | llvm-svn: 121878
* The new t2LEApcrel* pseudo instructions need the size specified.Jim Grosbach2010-12-151-5/+6
| | | | | | rdar://8768390 llvm-svn: 121876
* trailing whitespace.Jim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121789
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-17/+24
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-25/+16
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-16/+25
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
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