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* Provide a correct decoder hook for Thumb2 shifted registers. Found by ↵Owen Anderson2011-08-221-0/+1
| | | | | | randomized testing. llvm-svn: 138292
* Clean up predicates on ARM target instruction aliases.Jim Grosbach2011-08-221-12/+8
| | | | llvm-svn: 138249
* Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.Jim Grosbach2011-08-181-0/+28
| | | | llvm-svn: 137956
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-1/+1
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-0/+13
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-8/+8
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman2011-08-081-5/+6
| | | | | | correctly active without HasT2ExtractPack. PR10611. llvm-svn: 137061
* Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson2011-08-041-4/+7
| | | | llvm-svn: 136942
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-6/+2
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-2/+2
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM cleanup of remaining extend instructions.Jim Grosbach2011-07-271-115/+83
| | | | | | | | Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
* ARM extend instructions simplification.Jim Grosbach2011-07-271-28/+29
| | | | | | | | Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
* ARM rot_imm printing adjustment.Jim Grosbach2011-07-261-4/+4
| | | | | | | Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. llvm-svn: 136154
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-12/+10
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-251-1/+1
| | | | llvm-svn: 136006
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-251-2/+2
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-221-2/+2
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* ARM assembly parsing and encoding for SMC instruction.Jim Grosbach2011-07-221-1/+1
| | | | llvm-svn: 135782
* Tidy up a bit.Jim Grosbach2011-07-201-2/+2
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-201-13/+13
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-191-5/+4
| | | | | | Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-191-3/+3
| | | | | | | | Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
* ARM MCRR/MCRR2 immediate operand range checking.Jim Grosbach2011-07-141-1/+1
| | | | llvm-svn: 135192
* ARM MCR/MCR2 assembly parsing operand constraints.Jim Grosbach2011-07-141-4/+4
| | | | | | | The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-131-25/+25
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* ARM Assembler support for DBG instruction.Jim Grosbach2011-07-131-2/+1
| | | | | | Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
* Revert 135093. Think-o.Jim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135094
* Correct range for thumb co-processor immediateJim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135093
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-131-4/+4
| | | | llvm-svn: 135092
* Cleanup Thumb co-processor instructions a bit.Jim Grosbach2011-07-131-79/+35
| | | | | | Combine redundant base classes and such. No indended functional change. llvm-svn: 135085
* Parameterize away the ARM T1Cop class.Jim Grosbach2011-07-131-6/+10
| | | | llvm-svn: 135082
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-131-2/+89
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.Jim Grosbach2011-07-081-0/+11
| | | | llvm-svn: 134732
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-081-2/+3
| | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-011-43/+86
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-011-25/+11
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-301-16/+0
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-301-19/+4
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-57/+0
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* ARM Thumb2 asm syntax optional destination operand for binary operators.Jim Grosbach2011-06-281-9/+29
| | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 llvm-svn: 133973
* ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-271-0/+9
| | | | | | | | | | | Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. llvm-svn: 133966
* Reorg. No functionality change.Evan Cheng2011-06-211-23/+26
| | | | llvm-svn: 133533
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-211-22/+3
| | | | | | | | | | | | | | 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
* Add an alternative rev16 pattern. We should figure out a better way to ↵Evan Cheng2011-06-171-0/+6
| | | | | | handle these complex rev patterns. rdar://9609108 llvm-svn: 133289
* Another revsh pattern. rdar://9609059Evan Cheng2011-06-151-0/+4
| | | | llvm-svn: 133064
* Clean up a few 80 column violations.Jim Grosbach2011-06-131-23/+26
| | | | llvm-svn: 132946
* Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.Andrew Trick2011-06-071-2/+2
| | | | | | rdar://problem/9556069 llvm-svn: 132699
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-311-6/+6
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-281-2/+6
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
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