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* Thumb2 assembly parsing and encoding for MVN.Jim Grosbach2011-09-141-42/+47
| | | | llvm-svn: 139739
* Thumb2 assembly parsing and encoding for MSR/MRS.Jim Grosbach2011-09-141-27/+17
| | | | | | Fix a bug in handling default flags for both ARM and Thumb encodings. llvm-svn: 139721
* Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.Owen Anderson2011-09-131-2/+2
| | | | llvm-svn: 139639
* Zap some junk from the ARM instruction descriptions.Eli Friedman2011-09-131-20/+0
| | | | llvm-svn: 139575
* Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP ↵Owen Anderson2011-09-121-7/+88
| | | | | | either. llvm-svn: 139542
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-101-3/+16
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. llvm-svn: 139440
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-091-1/+3
| | | | llvm-svn: 139422
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-5/+6
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Thumb2 assembly parsing and encoding for LDRSB.Jim Grosbach2011-09-091-1/+11
| | | | llvm-svn: 139389
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-31/+32
| | | | llvm-svn: 139381
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-16/+28
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Thumb2 assembly parsing and encoding for LDR post-indexed.Jim Grosbach2011-09-081-24/+24
| | | | | | | More cleanup of the general indexed addressing T2 instructions. Still more to do, especially for stores. llvm-svn: 139272
* Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.Jim Grosbach2011-09-081-53/+58
| | | | | | | Adjust encoding of writeback load/store instructions to better reflect the way the operand types are represented. llvm-svn: 139270
* Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach2011-09-071-9/+17
| | | | llvm-svn: 139267
* Thumb2 assembly parsing and encoding for LDR(register).Jim Grosbach2011-09-071-0/+8
| | | | llvm-svn: 139264
* Thumb2 assembly parsing and encoding for LDRB(immediate).Jim Grosbach2011-09-071-3/+7
| | | | llvm-svn: 139258
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-071-0/+104
| | | | llvm-svn: 139256
* Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach2011-09-071-42/+52
| | | | | | | | | The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. llvm-svn: 139254
* Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.Jim Grosbach2011-09-071-2/+2
| | | | | | | | There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't documented as allowed). Also add the missing '!' token on the _UPD variant. llvm-svn: 139243
* Thumb2 use 'ldm' as default mnemonic.Jim Grosbach2011-09-071-2/+2
| | | | | | Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing). llvm-svn: 139234
* ISB is HasDB, not just HasV7.Jim Grosbach2011-09-061-1/+1
| | | | llvm-svn: 139202
* Thumb2 parsing and encoding for ISB.Jim Grosbach2011-09-061-8/+7
| | | | llvm-svn: 139200
* Thumb2 parsing and encoding for DMB.Jim Grosbach2011-09-061-0/+4
| | | | llvm-svn: 139193
* Thumb2 parsing and encoding for DBG.Jim Grosbach2011-09-061-6/+4
| | | | llvm-svn: 139191
* Thumb2 parsing and encoding for CMN and CMP.Jim Grosbach2011-09-061-21/+44
| | | | llvm-svn: 139188
* Thumb2 parsing and encoding for CLREX.Jim Grosbach2011-09-061-3/+1
| | | | llvm-svn: 139172
* Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng2011-09-061-17/+17
| | | | | | | | Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 llvm-svn: 139157
* Thumb2 parsing and encoding for BXJ.Jim Grosbach2011-09-021-6/+3
| | | | llvm-svn: 139053
* Thumb2 parsing and encoding for ASR.Jim Grosbach2011-09-021-12/+38
| | | | | | | For other shift and rotate instructions, too. Tests for those forthcoming as I work my way through the ISA. llvm-svn: 139040
* Tidy up. 80 columns.Jim Grosbach2011-09-021-4/+8
| | | | llvm-svn: 139022
* Thumb2 parsing and encoding for AND (register).Jim Grosbach2011-09-021-1/+21
| | | | llvm-svn: 139021
* Thumb2 parsing and encoding for ADD (register).Jim Grosbach2011-09-021-9/+14
| | | | llvm-svn: 139017
* Thumb2 assembly parsing and encoding for ADD(immediate).Jim Grosbach2011-09-011-0/+5
| | | | llvm-svn: 138922
* The asm parser currently selects the wrong encoding for non-conditional ↵Owen Anderson2011-08-311-1/+2
| | | | | | Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. llvm-svn: 138910
* Thumb2 parsing and encoding for ADC(register).Jim Grosbach2011-08-311-1/+22
| | | | | | | Also add instruction aliases for non-.w versions of SBC since they're the same. llvm-svn: 138871
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-301-2/+2
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Follow up to r138791.Evan Cheng2011-08-301-0/+2
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-301-49/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Revert 138781. It's not playing nicely with the immediate forms for ADC.Jim Grosbach2011-08-291-20/+0
| | | | llvm-svn: 138782
* Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.Jim Grosbach2011-08-291-0/+20
| | | | llvm-svn: 138781
* Thumb2 assembler parsing and encoding of IT instruction.Jim Grosbach2011-08-261-0/+7
| | | | | | | | This handles only the handling of the IT instruction itself, not the processing and validation of the instructions in the IT block. That's next, and will include encoding tests for IT itself. llvm-svn: 138665
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-261-0/+38
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* Perform more thorough checking of t2IT mask parameters, which fixes all ↵Owen Anderson2011-08-241-0/+1
| | | | | | remaining crashers when disassembling the entire 16-bit instruction space. llvm-svn: 138507
* Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson2011-08-241-0/+1
| | | | | | end up trying to print out an illegal predicate. llvm-svn: 138443
* Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson2011-08-231-0/+1
| | | | | | instructions. llvm-svn: 138339
* Fix two more instances of mis-matched operand names breaking disassembly. ↵Owen Anderson2011-08-231-6/+6
| | | | | | Found by randomized testing. llvm-svn: 138337
* t2SMLAD is a four-register instruction, not a three-register one.Owen Anderson2011-08-221-1/+1
| | | | llvm-svn: 138301
* Correct operand naming of t2USAT16 to allow proper decoding.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138300
* Match operand naming to allow correct decoding of t2LDRSH_POST.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138298
* Match operand names to provide correct decoding for Thumb2 SMULL.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138294
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