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* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-181-42/+42
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* whitespaceAndrew Trick2011-10-181-1/+1
| | | | llvm-svn: 142394
* Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.Jim Grosbach2011-10-181-0/+2
| | | | llvm-svn: 142363
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-181-1/+1
| | | | llvm-svn: 142332
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-171-2/+4
| | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> llvm-svn: 142294
* Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich2011-10-171-6/+6
| | | | | | lowered to. This fixes a lot of verifier failures on the test suite. llvm-svn: 142254
* Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.Cameron Zwarich2011-10-161-1/+3
| | | | | | | These missing flags show up as errors when running -verify-coalescing on test-suite. llvm-svn: 142111
* Fix an obvious typo found when looking at nearby code.Cameron Zwarich2011-10-161-1/+1
| | | | llvm-svn: 142110
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-73/+62
| | | | llvm-svn: 141811
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-101-0/+8
| | | | llvm-svn: 141591
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-101-8/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-071-0/+8
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-0/+2
| | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-031-18/+18
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. llvm-svn: 141020
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-5/+46
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-271-0/+10
| | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 llvm-svn: 140647
* Remove extraneous commit garbage.Owen Anderson2011-09-261-2/+0
| | | | llvm-svn: 140581
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-2/+18
| | | | llvm-svn: 140560
* Add more fixed bits to USAT16 encoding to filter out incorrect decodings.Owen Anderson2011-09-231-2/+2
| | | | llvm-svn: 140422
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-231-8/+8
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. llvm-svn: 140420
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-211-1/+0
| | | | | | other test failures I caused. llvm-svn: 140284
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-211-0/+2
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-35/+22
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-201-2/+4
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-4/+2
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
* Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.Jim Grosbach2011-09-201-0/+20
| | | | llvm-svn: 140125
* Remove incorrect comments. These are not disassmebly only patterns.Jim Grosbach2011-09-201-12/+6
| | | | llvm-svn: 140116
* Thumb2 range check on CPS mode immediate.Jim Grosbach2011-09-191-1/+1
| | | | llvm-svn: 140105
* Tidy up comments.Jim Grosbach2011-09-191-10/+5
| | | | llvm-svn: 140099
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-4/+22
| | | | llvm-svn: 140078
* Tidy up a bit.Jim Grosbach2011-09-191-4/+2
| | | | llvm-svn: 140050
* Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.Jim Grosbach2011-09-191-2/+14
| | | | llvm-svn: 140047
* Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the ↵Owen Anderson2011-09-191-0/+1
| | | | | | decoder from emitting gibberish for this invalid encoding. llvm-svn: 140041
* Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.Jim Grosbach2011-09-191-0/+8
| | | | llvm-svn: 140029
* Thumb2 assembly parsing and encoding for SUB(immediate).Jim Grosbach2011-09-161-0/+11
| | | | llvm-svn: 139966
* Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.Owen Anderson2011-09-161-0/+1
| | | | llvm-svn: 139958
* Thumb2 assembly parsing and encoding for STR.Jim Grosbach2011-09-161-21/+45
| | | | | | | More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). llvm-svn: 139949
* Tidy up. 80 columns.Jim Grosbach2011-09-161-6/+12
| | | | llvm-svn: 139944
* Thumb2 assembly parsing and encoding for STR(immediate).Jim Grosbach2011-09-161-0/+16
| | | | | | Add aliases for STRB/STRH while there. Tests forthcoming for those. llvm-svn: 139942
* Thumb2 assembly parsing and encoding for STMIA.Jim Grosbach2011-09-161-0/+3
| | | | llvm-svn: 139938
* Thumb2 assembly parsing and encoding for SSAT.Jim Grosbach2011-09-161-2/+9
| | | | llvm-svn: 139926
* Thumb2 assembly parsing and encoding for SRS.Jim Grosbach2011-09-161-20/+18
| | | | llvm-svn: 139925
* Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.Jim Grosbach2011-09-161-3/+3
| | | | llvm-svn: 139909
* Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.Jim Grosbach2011-09-161-4/+4
| | | | llvm-svn: 139906
* Remove incorrect comments.Jim Grosbach2011-09-151-3/+1
| | | | llvm-svn: 139877
* Thumb2 assembly parsing and encoding for RSB.Jim Grosbach2011-09-151-0/+13
| | | | llvm-svn: 139839
* Thumb2 assembly parsing and encoding for REV16/REVSH.Jim Grosbach2011-09-151-1/+3
| | | | llvm-svn: 139828
* Thumb2 assembly parsing and encoding for REV.Jim Grosbach2011-09-151-0/+2
| | | | llvm-svn: 139813
* Thumb2 push/pop mnemonic recognition.Jim Grosbach2011-09-151-0/+6
| | | | llvm-svn: 139794
* Thumb2 assembly parsing and encoding for PKH.Jim Grosbach2011-09-141-4/+14
| | | | llvm-svn: 139754
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