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* Revert commit r157966Joel Jones2012-06-051-24/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+24
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* Thumb2: RSB source register should be rGRP not GPRnopc.Jim Grosbach2012-05-211-4/+4
| | | | | | t2RSB defined the operand correctly, but tRSBS didn't. llvm-svn: 157200
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-171-2/+2
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-271-6/+6
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* Tidy up. 80 columns, whitespace, et. al.Jim Grosbach2012-04-231-4/+4
| | | | llvm-svn: 155399
* Fix a few more places in the ARM disassembler so that branches getKevin Enderby2012-04-121-0/+1
| | | | | | symbolic operands added when using the C disassembler API. llvm-svn: 154628
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-1/+2
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 llvm-svn: 154411
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-21/+3
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. llvm-svn: 154144
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-5/+23
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 llvm-svn: 154123
* Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.Jakob Stoklund Olesen2012-04-041-0/+2
| | | | | | | | | | A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-291-1/+2
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 llvm-svn: 153689
* Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ↵Evan Cheng2012-03-201-32/+23
| | | | | | t2PseudoExpand. llvm-svn: 153135
* ARM fix silly typo in optional operand alias.Jim Grosbach2012-03-161-1/+1
| | | | | | rdar://11065671 llvm-svn: 152954
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-161-0/+12
| | | | | | rdar://11058464 llvm-svn: 152883
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-0/+32
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-32/+0
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-0/+32
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Thumb2 asm aliases for wide bitwise w/ immediate instructions.Jim Grosbach2012-02-241-0/+9
| | | | llvm-svn: 151384
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-241-3/+1
| | | | | | | | | | | | | I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-0/+38
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Add missed mayStore flag to STREXD / t2STREXDAnton Korobeynikov2012-01-231-3/+2
| | | | llvm-svn: 148742
* Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.Jim Grosbach2012-01-211-0/+3
| | | | llvm-svn: 148601
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+29
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Replace FIXME with explanatory comment.Jim Grosbach2012-01-181-1/+2
| | | | llvm-svn: 148427
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-131-2/+3
| | | | | | | | | | The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-211-0/+5
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 llvm-svn: 147094
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-3/+3
| | | | llvm-svn: 146981
* Thumb2 ADR assembly parsing w/o the .w suffix.Jim Grosbach2011-12-151-0/+4
| | | | llvm-svn: 146710
* ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach2011-12-141-0/+2
| | | | llvm-svn: 146570
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-141-1/+6
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 llvm-svn: 146567
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-131-0/+7
| | | | | | rdar://10549767 llvm-svn: 146520
* Thumb2 pre/post indexed stores can be from any non-PC GPR.Jim Grosbach2011-12-131-3/+3
| | | | | | rdar://10549786 llvm-svn: 146518
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-131-0/+4
| | | | llvm-svn: 146511
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-091-0/+13
| | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-081-5/+13
| | | | llvm-svn: 146111
* Thumb2 alias for long-form pop and friends.Jim Grosbach2011-12-071-0/+12
| | | | | | rdar://10542474 llvm-svn: 146046
* Thumb2: MUL two-operand form encoding operand order fix.Jim Grosbach2011-12-061-1/+1
| | | | | | | | | Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 llvm-svn: 145922
* Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach2011-11-151-0/+5
| | | | | | rdar://10449724 llvm-svn: 144684
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-121-1/+1
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+6
| | | | | | rdar://10422955 llvm-svn: 144242
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-281-1/+13
| | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 llvm-svn: 143235
* Thumb2 ADD/SUB instructions encoding selection outside IT block.Jim Grosbach2011-10-281-0/+21
| | | | | | | | | | | Outside an IT block, "add r3, #2" should select a 32-bit wide encoding rather than generating an error indicating the 16-bit encoding is only legal in an IT block (outside, the 'S' suffic is required for the 16-bit encoding). rdar://10348481 llvm-svn: 143201
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-271-0/+6
| | | | | | rdar://10348844 llvm-svn: 143110
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-271-1/+3
| | | | | | rdar://10348584 llvm-svn: 143108
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-261-1/+16
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 llvm-svn: 143068
* Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach2011-10-261-1/+1
| | | | llvm-svn: 143034
* Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach2011-10-241-8/+4
| | | | | | PR11220 llvm-svn: 142801
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