summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMInstrThumb2.td
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-161-8/+27
| | | | | | | Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
* ARM: Fix incorrect pack pattern for thumb2Jim Grosbach2013-07-091-1/+6
| | | | | | | | | | | | | | | Propagate the fix from r185712 to Thumb2 codegen as well. Original commit message applies here as well: A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. rdar://14338767 llvm-svn: 185982
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-031-1/+1
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-261-13/+12
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-261-12/+10
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
* ARM: enable decoding of pc-relative PLD/PLIAmaury de la Vieuville2013-06-241-10/+33
| | | | llvm-svn: 184701
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-181-3/+3
| | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. llvm-svn: 184182
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-181-18/+31
| | | | llvm-svn: 184181
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-181-4/+12
| | | | | | | | This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one llvm-svn: 184180
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-141-1/+1
| | | | | | | was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! llvm-svn: 183975
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-1/+1
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-061-11/+15
| | | | | | Reapply 183264. llvm-svn: 183430
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-061-3/+6
| | | | | | Reapply 183262. llvm-svn: 183427
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-061-52/+86
| | | | | | Reapply of 183259. llvm-svn: 183421
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-107/+66
| | | | llvm-svn: 183273
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-041-11/+15
| | | | llvm-svn: 183264
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-041-3/+6
| | | | llvm-svn: 183262
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-041-52/+86
| | | | llvm-svn: 183259
* Tidy some register classes for ARM and ThumbJF Bastien2013-05-291-1/+1
| | | | | | | | | | | | | | | | | | Tidy up three places where the register class for ARM and Thumb wasn't restrictive enough: - No PC dest for reg-reg add/orr/sub. - No PC dest for shifts. - No PC or SP for Thumb2 reg-imm add. I encountered this while combining FastISel with -verify-machineinstrs. These instructions defined registers whose classes weren't restrictive enough, and the uses failed verification. They're also undefined in the ISA, or would produce code that FastISel wouldn't want. This doesn't fix the register class narrowing issue (where uses should restrict definitions), and isn't thorough, but it's a small step in the right direction. llvm-svn: 182863
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-261-11/+6
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-1/+1
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-101-1/+2
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-231-0/+7
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 llvm-svn: 175940
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-101-2/+4
| | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 llvm-svn: 169791
* The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem2012-11-141-6/+7
| | | | | | | | | | | is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 llvm-svn: 167963
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-101-14/+0
| | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 llvm-svn: 167657
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-1/+1
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-2/+2
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Fix a miscompilation caused by a typo. When turning a adde with negative valueEvan Cheng2012-10-241-1/+1
| | | | | | | | | into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 llvm-svn: 166613
* Add LLVM support for Swift.Bob Wilson2012-09-291-12/+14
| | | | llvm-svn: 164899
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-051-58/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-041-6/+25
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-281-54/+14
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-14/+54
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen2012-08-241-0/+1
| | | | | | | | | | It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. llvm-svn: 162603
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-161-0/+27
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-161-1/+1
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-151-1/+1
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-151-6/+9
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-121-25/+6
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-091-6/+25
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* ARM: More InstAlias refactors to use #NAME#.Jim Grosbach2012-08-021-42/+27
| | | | llvm-svn: 161220
* ARM: Refactor instaliases using TableGen support for #NAME#.Jim Grosbach2012-08-021-31/+23
| | | | | | | | Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. llvm-svn: 161218
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-0/+1
| | | | llvm-svn: 161159
* Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen2012-07-131-2/+2
| | | | | | | | | | | | Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
* Do not attempt to use ROR for Thumb1.Bob Wilson2012-07-021-2/+2
| | | | | | Patch by Matt Fischer! llvm-svn: 159538
* (sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng2012-06-231-0/+7
| | | | | | | | | | | | | | | There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-181-15/+12
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* This change handles a another case for generating the bic instruction Joel Jones2012-06-181-0/+31
| | | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> llvm-svn: 158659
* Re-enable the CMN instruction.Bill Wendling2012-06-111-13/+57
| | | | | | | | | We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
OpenPOWER on IntegriCloud