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* Fix a whole bunch of binary literals which were the wrong size. All were ↵Pete Cooper2014-08-071-2/+2
| | | | | | | | being silently zero extended to the correct width. The commit after this changes { } and 0bxx literals to be of type bits<n> and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us. llvm-svn: 215082
* Define stc2/stc2l/ldc2/ldc2l as thumb2 instructionsKeith Walker2014-08-051-4/+4
| | | | llvm-svn: 214868
* ARM: add patterns for [su]xta[bh] from just a shift.Tim Northover2014-07-231-0/+18
| | | | | | | | Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
* [ARM] Implement ISB memory barrier intrinsicYi Kong2014-07-031-4/+5
| | | | | | | Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-221-2/+2
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-141-0/+13
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* ARM: provide a new generic hint intrinsicSaleem Abdulrasool2014-04-251-1/+2
| | | | | | | | | Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into the instruction stream. This is particularly useful for generating IR from a compiler where the user may inject an intrinsic (e.g. __yield). These are then pattern substituted into the correct instruction which already existed. llvm-svn: 207242
* Fixed register class in STRD instruction for Thumb2 mode.Stepan Dyatkovskiy2014-04-041-1/+1
| | | | llvm-svn: 205612
* Tidy up. Trailing whitespace.Jim Grosbach2014-04-031-6/+6
| | | | llvm-svn: 205583
* ARM: add intrinsics for the v8 ldaex/stlexTim Northover2014-03-261-12/+30
| | | | | | | | | We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
* ARM: Thumb2 LDR(literal) can target SP.Jim Grosbach2014-02-111-1/+1
| | | | | | | | | Fix a slightly overzealous destination register restriction for the 'without .w' alias. Add some explicit testcases. rdar://16033140 llvm-svn: 201173
* ARM: use litpools for normal i32 imms when compiling minsize.Tim Northover2014-01-231-1/+1
| | | | | | | | | With constant-sharing, litpool loads consume 4 + N*2 bytes of code, but movw/movt pairs consume 8*N. This means litpools are better than movw/movt even with just one use. Other materialisation strategies can still be better though, so the logic is a little odd. llvm-svn: 199891
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-061-2/+2
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* ARM: remove special cases for Darwin dynamic-no-pic mode.Tim Northover2013-11-251-4/+0
| | | | | | | | | These are handled almost identically to static mode (and ELF's global address materialisation), except that a symbol may have "$non_lazy_ptr" appended. This can be handled by passing appropriate flags along with the instruction instead of using entirely separate pseudo-instructions. llvm-svn: 195655
* ARM: remove unused patterns.Tim Northover2013-11-251-2/+0
| | | | | | | | There is no sane way for an LEApcrel (= single ADR) instruction to generate a global address on any ARM target I know of. Fortunately, no-one was trying to any more, but there were vestigial patterns. llvm-svn: 195644
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-8/+21
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* ARM: permit bare dmb/dsb/isb aliases on Cortex-M0Tim Northover2013-11-051-3/+3
| | | | | | | | Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-291-1/+1
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-231-4/+4
| | | | llvm-svn: 193238
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-181-1/+1
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-1/+2
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* ARM: support interrupt attributeTim Northover2013-10-011-2/+5
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-2/+5
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-0/+9
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-231-3/+3
| | | | | | Patch by Bradley Smith. llvm-svn: 191202
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-181-0/+40
| | | | | | Patch by Bradley Smith! llvm-svn: 190928
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-1/+2
| | | | llvm-svn: 190862
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-2/+3
| | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-051-0/+14
| | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
* Reverting 190043 for now.Tilmann Scheller2013-09-051-1/+1
| | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. llvm-svn: 190047
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-051-1/+1
| | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! llvm-svn: 190043
* [ARMv8]Joey Gouly2013-08-281-11/+17
| | | | | | | | | | | Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. llvm-svn: 189490
* [ARMv8] Add a missing IsThumb to t2LDAEXD.Joey Gouly2013-08-281-1/+1
| | | | llvm-svn: 189482
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-271-12/+123
| | | | llvm-svn: 189388
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-72/+46
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-211-0/+3
| | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
* Thumb2 add immediate alias for SPMihai Popa2013-08-191-1/+2
| | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. llvm-svn: 188676
* Fix Thumb2 aliasing complementary instructions taking modified immediatesMihai Popa2013-08-161-4/+4
| | | | | | | | | | | | | | | | | | | | | There are many Thumb instructions which take 12-bit immediates encoded in a special 8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal to transform an assembly instruction to be able to encode the immediate. For example: AND and BIC are complementary instructions; one can switch the AND to a BIC as long as the immediate is complemented. The intent is to switch one instruction into its complementary one when the immediate cannot be encoded in the form requested in the original assembly and when the complementary immediate is encodable. The patch addresses two issues: 1. definition of t2SOImmNot immediate - it has to check that the orignal value is not encoded naturally 2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand rather than the ARM one. llvm-svn: 188548
* This fixes three issues related to Thumb literal loads:Mihai Popa2013-08-151-3/+3
| | | | | | | | | 1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020] 2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed 3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen and the ASM parser, so this alias rule really does nothing llvm-svn: 188466
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+5
| | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. llvm-svn: 188071
* Fix assembling of Thumb2 branch instructions.Mihai Popa2013-08-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. llvm-svn: 188067
* The name "tCDP" isn't used anywhere else in the source code, so renaming it ↵Mihai Popa2013-08-081-1/+1
| | | | | | | | | | for consistency doesn't cause any problems. This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards). Patch by Artyom Skrobov. llvm-svn: 187973
* This corrects creation of operands for t2PLDW. It also removes the ↵Mihai Popa2013-08-061-25/+22
| | | | | | | | definition of t2PLDWpci, as pldw does not have a literal variant (i.e. pc relative version) llvm-svn: 187804
* Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ↵Mihai Popa2013-08-061-4/+4
| | | | | | instead of apsr_nzcv) llvm-svn: 187803
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-311-0/+10
| | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 llvm-svn: 187530
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-221-1/+1
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-221-29/+13
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. llvm-svn: 186810
* ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.Tilmann Scheller2013-07-191-1/+6
| | | | | | | | See A8.8.127 in ARM DDI 0406C.b. Related to <rdar://problem/14403733>. llvm-svn: 186682
* ARM: Make sure the instruction alias for PLI uses the right subtarget features.Tilmann Scheller2013-07-181-1/+3
| | | | | | | | PLI requires both the Thumb2 and the ARMv7 feature. Related to <rdar://problem/14403733>. llvm-svn: 186620
* ARM: Add support for the Thumb2 PLI alternate literal form.Tilmann Scheller2013-07-161-0/+3
| | | | | | | | | | This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>] See A8.8.129 in the ARM ARM (DDI 0406C.b). Fixes <rdar://problem/14403733>. llvm-svn: 186459
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