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path: root/llvm/lib/Target/ARM/ARMInstrInfo.h
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* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-4/+5
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-9/+9
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+4
| | | | llvm-svn: 59542
* Handle the rest of pseudo instructions.Evan Cheng2008-11-131-24/+24
| | | | llvm-svn: 59275
* Fix pre- and post-indexed load / store encoding bugs.Evan Cheng2008-11-131-16/+18
| | | | llvm-svn: 59230
* Fix address mode 3 immediate offset mode encoding.Evan Cheng2008-11-121-0/+2
| | | | llvm-svn: 59109
* Consolidate formats; fix FCMPED etc. encodings.Evan Cheng2008-11-121-25/+22
| | | | llvm-svn: 59107
* Fix VFP conversion instruction encodings.Evan Cheng2008-11-121-4/+6
| | | | llvm-svn: 59104
* Fix FMDRR encoding.Evan Cheng2008-11-111-4/+5
| | | | llvm-svn: 59088
* Encode VFP load / store instructions.Evan Cheng2008-11-111-22/+24
| | | | llvm-svn: 59084
* Encode VFP conversion instructions.Evan Cheng2008-11-111-4/+4
| | | | llvm-svn: 59074
* Encode VFP arithmetic instructions.Evan Cheng2008-11-111-4/+11
| | | | llvm-svn: 59016
* Encode misc arithmetic instructions.Evan Cheng2008-11-071-0/+1
| | | | llvm-svn: 58828
* Encode extend instructions; more clean up.Evan Cheng2008-11-061-14/+20
| | | | llvm-svn: 58818
* - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.Evan Cheng2008-11-061-2/+2
| | | | | | | - Consolidate instruction formats. - Other clean up. llvm-svn: 58808
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 ↵Evan Cheng2008-11-061-6/+2
| | | | | | encoding bug. llvm-svn: 58800
* Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.Evan Cheng2008-11-061-18/+14
| | | | llvm-svn: 58793
* Fix encoding of multiple instructions with 3 src operands; also handle ↵Evan Cheng2008-11-061-19/+18
| | | | | | smmul, smmla, and smmls. llvm-svn: 58789
* Restructure ARM code emitter to use instruction formats instead of ↵Evan Cheng2008-11-051-37/+37
| | | | | | addressing modes to determine how to encode instructions. llvm-svn: 58764
* Add binary encoding support for multiply instructions. Some blanks left to ↵Jim Grosbach2008-11-031-15/+17
| | | | | | fill in, but the basics are there. llvm-svn: 58626
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-5/+5
| | | | llvm-svn: 57622
* need ARM.h for ARMCC definitionJim Grosbach2008-10-071-0/+1
| | | | llvm-svn: 57261
* Encode the conditional execution predicate when JITing.Jim Grosbach2008-10-071-0/+6
| | | | llvm-svn: 57258
* Revert 56176. All those instruction formats are still needed.Evan Cheng2008-09-131-7/+23
| | | | llvm-svn: 56180
* Eliminate unnecessary instruction formats.Evan Cheng2008-09-121-23/+7
| | | | llvm-svn: 56176
* Rewrite address mode 1 code emission routines.Evan Cheng2008-09-121-0/+1
| | | | llvm-svn: 56171
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-1/+1
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-6/+7
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Make LiveVariables even more optional, by making it optional in the call to ↵Owen Anderson2008-07-021-1/+1
| | | | | | | | TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-141-1/+1
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-10/+4
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-0/+3
| | | | llvm-svn: 48995
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+4
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+14
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-0/+6
| | | | llvm-svn: 45603
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+19
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+5
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* Fix a misnamed parameter.Christopher Lamb2007-10-181-1/+1
| | | | llvm-svn: 43145
* Instruction formats added used to generate multiply instructions of V5TE.Raul Herbster2007-08-301-39/+52
| | | | llvm-svn: 41629
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-071-1/+49
| | | | llvm-svn: 40887
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-0/+3
| | | | | | the 's' bit. llvm-svn: 38501
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-1/+0
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-0/+1
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-2/+0
| | | | llvm-svn: 37643
* Instructions with unique labels or embedded jumptables cannot be duplicated ↵Evan Cheng2007-06-151-0/+2
| | | | | | during ifcvt. llvm-svn: 37606
* Add missing const qualifiers.Evan Cheng2007-05-291-5/+7
| | | | llvm-svn: 37342
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