summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMInstrInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [arm] Implement Target Operand Flag MIR serialization.Evgeniy Stepanov2018-01-111-0/+28
| | | | | | | | | | Reviewers: efriedma, pcc Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D39975 llvm-svn: 322312
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-2/+2
| | | | | | | | | In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-2/+2
| | | | | | This broke almost all bots. Reverting while fixing. llvm-svn: 301041
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-211-2/+2
| | | | | | | | | | | | | | | | | | Empty functions can lead to duplicate entries in the Guard CF Function Table of a binary due to multiple functions sharing the same RVA, causing the kernel to refuse to load that binary. We had a terrific bug due to this in Chromium. It turns out we were already doing this for Mach-O in certain situations. This patch expands the code for that in AsmPrinter::EmitFunctionBody() and renames TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it seems it was used for not just Mach-O anyway. Differential Revision: https://reviews.llvm.org/D32330 llvm-svn: 301040
* [ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus2017-01-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Replace all uses of AddDefaultPred with MachineInstrBuilder::add(predOps()). This makes the code building MachineInstrs more readable, because it allows us to write code like: MIB.addSomeOperand(blah) .add(predOps()) .addAnotherOperand(blahblah) instead of AddDefaultPred(MIB.addSomeOperand(blah)) .addAnotherOperand(blahblah) This commit also adds the predOps helper in the ARM backend, as well as the add method taking a variable number of operands to the MachineInstrBuilder. The transformation has been done mostly automatically with a custom tool based on Clang AST Matchers + RefactoringTool. Differential Revision: https://reviews.llvm.org/D28555 llvm-svn: 291890
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-1/+3
| | | | | | | | | | | | | | | | | | | Summary: An IR load can be invariant, dereferenceable, neither, or both. But currently, MI's notion of invariance is IR-invariant && IR-dereferenceable. This patch splits up the notions of invariance and dereferenceability at the MI level. It's NFC, so adds some probably-unnecessary "is-dereferenceable" checks, which we can remove later if desired. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23371 llvm-svn: 281151
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-151-2/+2
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* Don't pass a Reloc::Model to GVIsIndirectSymbol.Rafael Espindola2016-06-281-2/+1
| | | | | | | | It already has access to it. While at it, rename it to isGVIndirectSymbol. llvm-svn: 274023
* Don't pass Reloc::Model to places that already have it. NFC.Rafael Espindola2016-06-281-8/+9
| | | | llvm-svn: 274022
* ARM/ELF: Better codegen for global variable addresses.Peter Collingbourne2015-10-261-70/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC mode we were previously computing global variable addresses (or GOT entry addresses) by adding the PC, the PC-relative GOT displacement and the GOT-relative symbol/GOT entry displacement. Because the latter two displacements are fixed, we ended up performing one more addition than necessary. This change causes us to compute addresses using a single PC-relative displacement, resulting in a shorter code sequence. This reduces code size by about 4% in a recent build of Chromium for Android. As a result of this change we no longer need to compute the GOT base address in the ARM backend, which allows us to remove the Global Base Reg pass and SDAG lowering for the GOT. We also now no longer use the GOT when addressing a symbol which is known to be defined in the same linkage unit. Specifically, the symbol must have either hidden visibility or a strong definition in the current module in order to not use the the GOT. This is a change from the previous behaviour where we would use the GOT to address externally visible symbols defined in the same module. I think the only cases where this could matter are cases involving symbol interposition, but we don't really support that well anyway. Differential Revision: http://reviews.llvm.org/D13650 llvm-svn: 251322
* ARMInstrInfo.cpp: Reformat.NAKAMURA Takumi2015-09-221-66/+65
| | | | llvm-svn: 248260
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | This commit removes the global manager variable which is responsible for storing and allocating pseudo source values and instead it introduces a new manager class named 'PseudoSourceValueManager'. Machine functions now own an instance of the pseudo source value manager class. This commit also modifies the 'get...' methods in the 'MachinePointerInfo' class to construct pseudo source values using the instance of the pseudo source value manager object from the machine function. This commit updates calls to the 'get...' methods from the 'MachinePointerInfo' class in a lot of different files because those calls now need to pass in a reference to a machine function to those methods. This change will make it easier to serialize pseudo source values as it will enable me to transform the mips specific MipsCallEntry PseudoSourceValue subclass into two target independent subclasses. Reviewers: Akira Hatanaka llvm-svn: 244693
* Move most user of TargetMachine::getDataLayout to the Module oneMehdi Amini2015-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. This patch is quite boring overall, except for some uglyness in ASMPrinter which has a getDataLayout function but has some clients that use it without a Module (llmv-dsymutil, llvm-dwarfdump), so some methods are taking a DataLayout as parameter. Reviewers: echristo Subscribers: yaron.keren, rafael, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11090 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242386
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-8/+8
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-121-2/+1
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Cleanup and remove a chunk of getARMSubtarget calls in theEric Christopher2015-03-051-0/+4
| | | | | | | ARM TargetMachine pass pipeline construction by pushing them down into the appropriate pass. llvm-svn: 231323
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-1/+1
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 229999
* Remove calls to bare getSubtarget and clean up the functionsEric Christopher2015-01-301-9/+6
| | | | | | accordingly. llvm-svn: 227535
* Migrate ARM except for TTI, AsmPrinter, and frame loweringEric Christopher2015-01-291-5/+5
| | | | | | away from getSubtargetImpl. llvm-svn: 227399
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-3/+2
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* [ARM, stack protector] If supported, use armv7 instructions.Akira Hatanaka2014-10-231-4/+39
| | | | | | | | | | | | | | | | | This commit enables using movt/movw to load the stack guard address: movw r0, :lower16:(L_g3$non_lazy_ptr-(LPC0_0+8)) movt r0, :upper16:(L_g3$non_lazy_ptr-(LPC0_0+8)) ldr r0, [pc, r0] Previously a pc-relative load was emitted: ldr r0, LCPI0_0 ldr r0, [pc, r0] rdar://problem/18740489 llvm-svn: 220470
* [ARM] Move the implementation of the target hooks related to copy-relatedQuentin Colombet2014-08-221-69/+0
| | | | | | | | | instruction from ARMInstrInfo to ARMBaseInstrInfo. That way, thumb mode can also benefit from the advanced copy optimization. <rdar://problem/12702965> llvm-svn: 216274
* [ARM] Mark VSETLNi32 with the InsertSubreg property and implement the relatedQuentin Colombet2014-08-211-0/+23
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VSETLNi32 dY, rZ, imm is the same as: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(imm) <rdar://problem/12702965> llvm-svn: 216143
* [ARM] Mark VMOVRRD with the ExtractSubreg property and implement the relatedQuentin Colombet2014-08-201-0/+21
| | | | | | | | | | | | | | target hook. This patch teaches the compiler that: rX, rY = VMOVRRD dZ is the same as: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1 <rdar://problem/12702965> llvm-svn: 216132
* [ARM] Mark VMOVDRR with the RegSequence property and implement the relatedQuentin Colombet2014-08-111-0/+25
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VMOVDRR rY, rZ is the same as: dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1 <rdar://problem/12702965> llvm-svn: 215404
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectlyAkira Hatanaka2014-08-021-3/+3
| | | | | | | | | expanding pseudo LOAD_STATCK_GUARD using instructions that are normally used in pic mode. This patch fixes the bug. <rdar://problem/17886592> llvm-svn: 214614
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+8
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-3/+3
| | | | | | class. llvm-svn: 203433
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
| | | | | | | | | | | | | | We were figuring out whether to use tPICADD or PICADD, then just using tPICADD unconditionally anyway. Oops. A testcase from someone familiar enough with ELF to produce one would be appreciated. The existing PIC testcase correctly verifies the .s generated, but that doesn't catch this bug, which only showed up in direct-to-object mode. http://llvm.org/bugs/show_bug.cgi?id=17180 llvm-svn: 190417
* ARM: Fix ELF global base reg intialization.Jim Grosbach2013-08-261-3/+8
| | | | | | | | | | | | | | | | | | The create machine code wasn't properly in SSA, which the machine verifier properly complains about. Now that fast-isel is closer to verifier clean, errors like this show up more clearly. Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb mode functions, which is obviously wrong. Fix that along the way. Test case is part of the following commit which will finish making an additional fast-isel test verifier clean an enable it for the regression test suite. This commit is separate since its not just a verifier cleanup, but an actual correctness issue. rdar://12594152 (for the fast-isel verifier aspects) llvm-svn: 189269
* When initializing the PIC global base register on ARM/ELF add pc to fix the ↵Benjamin Kramer2013-08-161-0/+4
| | | | | | | | | | address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
| | | | | | | | | | | | | | do in the SDag when lowering references to the GOT: use ARMConstantPoolSymbol rather than creating a dummy global variable. The computation of the alignment still feels weird (it uses IR types and datalayout) but it preserves the exact previous behavior. This change fixes the memory leak of the global variable detected on the valgrind leak checking bot. Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to handle this use case. llvm-svn: 187303
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+62
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-181-1/+2
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+17
| | | | | | | | | | | | | | Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 llvm-svn: 151673
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-2/+4
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-6/+12
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+0
| | | | llvm-svn: 134024
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-121-24/+0
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-291-2/+1
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+2
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-1/+1
| | | | | | rdar://8477752. llvm-svn: 117419
OpenPOWER on IntegriCloud