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* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-31/+32
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* ARMv4 JIT forgets to set the lr register when making a indirect function ↵Xerxes Ranby2010-07-221-1/+1
| | | | | | call. Fixes PR7608 llvm-svn: 109125
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-261-12/+12
| | | | llvm-svn: 106927
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-251-18/+18
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
* Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson2010-06-251-5/+1
| | | | | | Renumber MiscFrm to 25. llvm-svn: 106916
* Clean up some extra whitespace.Bob Wilson2010-05-241-12/+12
| | | | llvm-svn: 104544
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-14/+11
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.Johnny Chen2010-03-291-0/+1
| | | | | | | | | | | | | These instructions use byte index in a control vector (M:Vm) to lookup byte values in a table and generate a new vector (D:Vd). The table is specified via a list of vectors, which can be: {Dn} {Dn D<n+1>} {Dn D<n+1> D<n+2>} {Dn D<n+1> D<n+2> D<n+3>} llvm-svn: 99789
* Add a format argument to the N3V and N3VX classes, removing the N3Vf class.Bob Wilson2010-03-271-13/+6
| | | | llvm-svn: 99704
* Add NVMulSLFrm to represent "3-register multiply with scalar" operations and setJohnny Chen2010-03-271-0/+1
| | | | | | | | | | | | it as the format for the appropriate N3V*SL*<> classes. These instructions require special handling of the M:Vm field which encodes the restricted Dm and the lane index within Dm. Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar): vmlal.s32 q3, d2, d10[0] llvm-svn: 99690
* Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}Johnny Chen2010-03-261-0/+1
| | | | | | | | | to encode the byte location of the extracted result in the concatenation of the operands, from the least significant end. Modify VEXTd and VEXTq classes to use the format. llvm-svn: 99659
* Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do notJohnny Chen2010-03-261-5/+13
| | | | | | | | | | | | | | follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand). Add a parent class N3Vf which requires passing a Format argument and which the N3V class is modified to inherit from. N3V class represents the "normal" 3-Register NEON Instructions with N3RegFrm. Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift Instructions and replace 8 invocations with it. llvm-svn: 99655
* Add N3RegFrm to represent "NEON 3 vector register format" instructions.Johnny Chen2010-03-261-2/+3
| | | | | | | Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference). llvm-svn: 99628
* Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easilyJohnny Chen2010-03-261-0/+2
| | | | | | | | | | | dispatch to the appropriate routines to handle the different interpretations of the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted the same between the two, though. See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format. llvm-svn: 99590
* Removed instruction class NI from ARMInstrFormats.td.Johnny Chen2010-03-251-6/+0
| | | | | | It doesn't seem to be used anywhere. llvm-svn: 99566
* Add NVDupLnFrm and change NVDupLane class to use that format.Johnny Chen2010-03-251-1/+2
| | | | llvm-svn: 99557
* Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm toJohnny Chen2010-03-251-5/+6
| | | | | | expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format. llvm-svn: 99548
* Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,Johnny Chen2010-03-251-0/+13
| | | | | | | instead of the current N2V. Format of NVDupLane instances are set to NEONFrm currently. llvm-svn: 99518
* Make the use of the vmla and vmls VFP instructions controllable via cmd line.Jim Grosbach2010-03-241-0/+14
| | | | | | | Preliminary testing shows significant performance wins by not using these instructions. llvm-svn: 99436
* Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.Johnny Chen2010-03-241-1/+0
| | | | | | NVCVTFrm will later be used to describe "vcvt with fractional bits". llvm-svn: 99415
* Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,Johnny Chen2010-03-241-6/+6
| | | | | | respectively, and add some more comment. llvm-svn: 99373
* Renamed NVdImmFrm to N1RegModImmFrm.Johnny Chen2010-03-231-2/+2
| | | | llvm-svn: 99344
* Fix typo in the comment for N3VX class.Johnny Chen2010-03-231-1/+1
| | | | llvm-svn: 99328
* Add New NEON Format NVdVmVCVTFrm.Johnny Chen2010-03-231-0/+1
| | | | | | Converted some of the NEON vcvt instructions to this format. llvm-svn: 99326
* Add New NEON Format NVdVmImmFrm.Johnny Chen2010-03-231-11/+13
| | | | llvm-svn: 99322
* Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.Bob Wilson2010-03-231-6/+0
| | | | | | | | | | These instructions are only needed for codegen, so I've removed all the explicit encoding bits for now; they should be set in the same way as the for VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5 requires that the instructions be custom-selected so that the number of registers can be set in the AM5Opc value. llvm-svn: 99309
* Fix bad indentation, 80-column violations, and trailing whitespace.Bob Wilson2010-03-231-52/+60
| | | | llvm-svn: 99295
* Add New NEON Format NVdImmFrm.Johnny Chen2010-03-231-7/+8
| | | | | | Ref: A7.4.6 One register and a modified immediate value. llvm-svn: 99288
* Add NLdStFrm Format.Johnny Chen2010-03-201-6/+9
| | | | llvm-svn: 99014
* Revert this change, since it was causing ARM performance regressions.Bob Wilson2010-03-191-3/+0
| | | | | | | | | | | | --- Reverse-merging r98889 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMISelLowering.h U lib/Target/ARM/ARMInstrInfo.td U lib/Target/ARM/ARMInstrVFP.td U lib/Target/ARM/ARMISelLowering.cpp U lib/Target/ARM/ARMInstrFormats.td llvm-svn: 99010
* Renumber LdStExFrm from 28 to 11 and shift the existing format values to makeJohnny Chen2010-03-191-22/+22
| | | | | | | room for it. This is in preparation for another patch which is adding NEON subformats to facilitate disassembly. llvm-svn: 98967
* Update comment to refer to the right filename.Bob Wilson2010-03-181-1/+1
| | | | llvm-svn: 98902
* Get rid of target-specific fp <-> int nodes when still I'm here.Anton Korobeynikov2010-03-181-0/+3
| | | | llvm-svn: 98889
* fix some buggy ops concatentationChris Lattner2010-03-181-12/+12
| | | | llvm-svn: 98869
* Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.Johnny Chen2010-03-171-43/+0
| | | | | | There is a better way coming up. llvm-svn: 98777
* Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3fBob Wilson2010-03-171-3/+3
| | | | | | in svn r74988 but the format field was never widened. llvm-svn: 98768
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-171-0/+43
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-43/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-0/+43
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Attempt to appease the arm-linux buildbot by fixing the JIT encodings for newBob Wilson2010-03-131-8/+9
| | | | | | base register updating load/store-multiple instructions. llvm-svn: 98427
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-10/+14
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* Factored out the disassembly printing of CPS option, MSR mask, and Negative ZeroJohnny Chen2010-03-101-0/+17
| | | | | | | operands into their own PrintMethod, in order not to pollute the printOperand() impl with disassembly only Imm modifiers. llvm-svn: 98172
* Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the WJohnny Chen2010-03-011-1/+1
| | | | | | bit should be set to 0 instead of 1. llvm-svn: 97481
* Added the follwoing 32-bit Thumb instructions for disassembly only:Johnny Chen2010-02-261-0/+13
| | | | | | | | | | | | o Parallel addition and subtraction, signed/unsigned o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8 o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16 o Signed multiply accumulate long (halfwords): SMLAL<x><y> o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X] o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X] llvm-svn: 97276
* Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.Johnny Chen2010-02-181-0/+53
| | | | llvm-svn: 96619
* Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errorsJohnny Chen2010-02-181-3/+3
| | | | | | of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process. llvm-svn: 96565
* Add YIELD, WFE, WFI, and SEV instructions for disassembly only.Johnny Chen2010-02-121-0/+3
| | | | | | | Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly only instructions are changed from Pseudo Format to MiscFrm Format. llvm-svn: 96032
* Forgot to also check in this file for vcvt (floating-point <-> fixed-point, ↵Johnny Chen2010-02-111-0/+9
| | | | | | | | VFP). Sorry! llvm-svn: 95892
* Modified encoding bits specification for VFP instructions. In particular, the DJohnny Chen2010-01-291-32/+47
| | | | | | | bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary format instructions, Inst{6} and Inst{4} need to specified for proper decodings. llvm-svn: 94855
* Add encoding bits for some Thumb instructions. Plus explicitly set the top twoJohnny Chen2009-12-161-8/+11
| | | | | | bytes of Inst to 0x0000 for the benefit of the Thumb decoder. llvm-svn: 91496
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