summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMInstrFormats.td
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM STRH encoding information.Jim Grosbach2010-11-111-7/+12
| | | | llvm-svn: 118757
* Move LDM predicate operand encoding into base clase. Add STM missing STMJim Grosbach2010-11-101-2/+10
| | | | | | encoding bits. llvm-svn: 118738
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-101-1/+3
| | | | llvm-svn: 118736
* Fix ARM encoding of non-return LDM instructions.Jim Grosbach2010-11-101-1/+1
| | | | llvm-svn: 118732
* Fix ARM encoding of LDM+Return instruction.Jim Grosbach2010-11-101-2/+4
| | | | llvm-svn: 118730
* Add encoding for VSTR.Bill Wendling2010-11-041-0/+22
| | | | llvm-svn: 118220
* Revert r118097 to fix buildbots.Owen Anderson2010-11-021-4/+4
| | | | llvm-svn: 118121
* Since these fields are not exactly equivalent to the encoded field, rename ↵Owen Anderson2010-11-021-4/+4
| | | | | | them to something with semantic meaning. llvm-svn: 118097
* Factor out a common encoding class for loads and stores with a lane parameter.Owen Anderson2010-11-021-0/+8
| | | | llvm-svn: 118055
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-021-0/+9
| | | | llvm-svn: 117984
* Move the machine operand MC encoding patterns to the parent classes.Bill Wendling2010-11-011-0/+13
| | | | llvm-svn: 117956
* Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach2010-11-011-6/+6
| | | | | | | codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
* Move instruction encoding bits into the parent class and remove the temporaryBill Wendling2010-11-011-0/+59
| | | | | | | *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. llvm-svn: 117906
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-311-0/+3
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-301-0/+4
| | | | llvm-svn: 117753
* ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj ↵Jim Grosbach2010-10-291-0/+13
| | | | | | pseudos and a FIXME for TLS. llvm-svn: 117702
* ARM mode LDREX*/STREX* binary encodings.Jim Grosbach2010-10-291-0/+10
| | | | llvm-svn: 117695
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-4/+5
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson2010-10-271-5/+6
| | | | llvm-svn: 117495
* Provide correct NEON encodings for vdup.Owen Anderson2010-10-271-0/+18
| | | | llvm-svn: 117475
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+33
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Provide correct NEON encodings for vshl, register and immediate forms.Owen Anderson2010-10-261-0/+11
| | | | llvm-svn: 117394
* Add NEON encodings for vmov and vmvn of immediates.Owen Anderson2010-10-261-0/+10
| | | | llvm-svn: 117374
* NEON vmov's are in Neon domain.Evan Cheng2010-10-261-1/+1
| | | | llvm-svn: 117347
* Add correct instruction encodings for vbic, vorn, and vmvn.Owen Anderson2010-10-251-0/+18
| | | | llvm-svn: 117282
* Provide correct NEON encodings for vand, veor, and vorr.Owen Anderson2010-10-251-0/+12
| | | | llvm-svn: 117279
* ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.Jim Grosbach2010-10-221-2/+27
| | | | llvm-svn: 117165
* More ARM multiply instuction binary encodings.Jim Grosbach2010-10-221-1/+28
| | | | llvm-svn: 117121
* Parameterize a bit of ARM encoding information, simplifying some instructionJim Grosbach2010-10-221-2/+3
| | | | | | definitions. llvm-svn: 117114
* More ARM multiply instruction encoding information.Jim Grosbach2010-10-221-3/+16
| | | | llvm-svn: 117108
* ARM encodes Q registers as 2xregno (i.e. the number of the D register that ↵Owen Anderson2010-10-211-0/+12
| | | | | | | | | corresponds to the lower half of the Q register), rather than with just regno. This allows us to unify the encodings for a lot of different NEON instrucitons that differ only in whether they have Q or D register operands. llvm-svn: 117056
* ARM instructions that are both predicated and set the condition codesBob Wilson2010-10-151-1/+1
| | | | | | | | | | have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! llvm-svn: 116563
* trailing whitespaceJim Grosbach2010-10-131-1/+1
| | | | llvm-svn: 116450
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+3
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+6
| | | | llvm-svn: 116421
* Add custom encoder for the 's' bit denoting whether an ARM arithmeticJim Grosbach2010-10-121-2/+4
| | | | | | | instruction should set the processor status flags or not. Remove the now unnecessary special handling for the bit from the MCCodeEmitter. llvm-svn: 116360
* Split out the "size" field from the encoding. The newer documentation has it asBill Wendling2010-10-121-9/+18
| | | | | | a separate bit in the coding. llvm-svn: 116347
* Encoding for ARM-mode VADD.F32 instruction.Jim Grosbach2010-10-121-0/+2
| | | | llvm-svn: 116338
* More binary encoding stuff, taking advantage of the new "by name" operandJim Grosbach2010-10-111-0/+7
| | | | | | matching in tblgen to do the predicate operand. llvm-svn: 116213
* Add a 'pattern' arg to the ARM PseudoNeonI class.Jim Grosbach2010-10-061-1/+3
| | | | llvm-svn: 115831
* replace stuff like:Chris Lattner2010-10-061-15/+11
| | | | | | | | | | | | | | let AsmString = !strconcat( !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), !strconcat("\t", asm)); with: let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); :) llvm-svn: 115720
* Increase the number of bits used internally by the ARM target to represent theJim Grosbach2010-10-051-9/+9
| | | | | | addressing mode from four to five. llvm-svn: 115645
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-161-0/+11
| | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. llvm-svn: 114047
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-0/+8
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* VFP/NEON load/store multiple instructions are addrmode4, not 5.Jim Grosbach2010-09-081-4/+4
| | | | llvm-svn: 113322
* - Cleanup some whitespaces.Bill Wendling2010-08-311-102/+101
| | | | | | - Convert {0,1} and friends into 0b01, which is identical and more consistent. llvm-svn: 112593
* Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, whichBill Wendling2010-08-301-21/+0
| | | | | | | is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this out! :-) llvm-svn: 112538
* Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is theBill Wendling2010-08-301-3/+24
| | | | | | | | optional modified register (instead of reg0). Along with r112461 it will make sure that the optional define of CPSR is marked as "def" and will thus mark the instructions using these classes (t2ANDS*) as setting the 's' flag. llvm-svn: 112462
* Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson2010-08-251-0/+8
| | | | | | | | | | | with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. llvm-svn: 112108
* MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar2010-08-111-0/+6
| | | | llvm-svn: 110788
OpenPOWER on IntegriCloud