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* Trailing whitespace.Jim Grosbach2010-12-101-5/+5
| | | | llvm-svn: 121521
* Fix Thumb2 encoding of the S bit.Owen Anderson2010-12-071-0/+3
| | | | llvm-svn: 121182
* The ARM AsmMatcher needs to know that the CCOut operand is a register value,Jim Grosbach2010-12-061-0/+7
| | | | | | not an immediate. It stores either ARM::CPSR or reg0. llvm-svn: 121018
* Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling2010-12-011-1/+5
| | | | | | encoding if we're in that mode. llvm-svn: 120608
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-0/+9
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* General cleanups of comments.Bill Wendling2010-12-011-11/+7
| | | | llvm-svn: 120536
* s/T1pIEncode/T1pILdStEncode/gBill Wendling2010-12-011-6/+6
| | | | | | s/T1pIEncodeImm/T1pILdStEncodeImm/g llvm-svn: 120524
* Renaming variables to coincide with documentation. No functionality change.Bill Wendling2010-12-011-1/+1
| | | | llvm-svn: 120522
* Rename operands to match ARM documentation. No functionality change.Bill Wendling2010-11-301-2/+2
| | | | llvm-svn: 120500
* Inline classes that were used in only one place.Bill Wendling2010-11-301-5/+2
| | | | llvm-svn: 120488
* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-301-12/+31
| | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. llvm-svn: 120482
* Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.Jim Grosbach2010-11-301-13/+0
| | | | | | rdar://8685712 llvm-svn: 120438
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-301-0/+9
| | | | llvm-svn: 120364
* Parameterize ARMPseudoInst size property.Jim Grosbach2010-11-291-4/+2
| | | | llvm-svn: 120353
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-291-3/+7
| | | | llvm-svn: 120310
* Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.Jim Grosbach2010-11-291-0/+18
| | | | llvm-svn: 120303
* trailing whitespaceJim Grosbach2010-11-191-16/+16
| | | | llvm-svn: 119863
* Add ARM encoding information for STRD.Jim Grosbach2010-11-191-15/+2
| | | | llvm-svn: 119852
* Factor out operand encoding bits for ARM addressing mode 2 store instructions.Jim Grosbach2010-11-191-1/+17
| | | | llvm-svn: 119846
* Delete another dead class.Jim Grosbach2010-11-191-12/+0
| | | | llvm-svn: 119844
* whitespace tweak.Jim Grosbach2010-11-191-1/+0
| | | | llvm-svn: 119843
* Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.Jim Grosbach2010-11-191-43/+0
| | | | llvm-svn: 119841
* Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.Jim Grosbach2010-11-191-2/+2
| | | | llvm-svn: 119840
* Add ARM binary encoding information for the rest of the indexed loads.Jim Grosbach2010-11-191-126/+15
| | | | llvm-svn: 119821
* Remove dead code.Jim Grosbach2010-11-191-10/+0
| | | | llvm-svn: 119815
* ARM LDRD binary encoding.Jim Grosbach2010-11-191-17/+3
| | | | llvm-svn: 119812
* Add ARM encoding information for LDRH post-increment.Jim Grosbach2010-11-181-7/+13
| | | | llvm-svn: 119743
* Fill out the set of Thumb2 multiplication operator encodings.Owen Anderson2010-11-181-13/+0
| | | | llvm-svn: 119733
* ARMPseudoInst instructions should default to being considered a single 4-byteJim Grosbach2010-11-181-0/+3
| | | | | | | instruction. Any that may be expanded otherwise by MC lowering should override this value. rdar://8683274 llvm-svn: 119713
* ARM PseudoInst instructions don't need or use an assembler string. Get rid ofJim Grosbach2010-11-181-5/+3
| | | | | | the operand to the pattern. llvm-svn: 119607
* Add FIXME.Jim Grosbach2010-11-181-0/+3
| | | | llvm-svn: 119603
* Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and notJim Grosbach2010-11-181-19/+8
| | | | | | just pretend to be. llvm-svn: 119602
* Refactor a few ARM load instructions to better parameterize things and re-useJim Grosbach2010-11-181-74/+10
| | | | | | common encoding information. llvm-svn: 119598
* More ARM encoding bits. LDRH now encodes properly.Jim Grosbach2010-11-171-21/+38
| | | | llvm-svn: 119529
* Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling2010-11-171-1/+23
| | | | | | | "getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. llvm-svn: 119435
* - Remove dead patterns.Bill Wendling2010-11-161-32/+0
| | | | | | - Add encodings to the *LDMIA_RET instrs. Probably not needed... llvm-svn: 119323
* ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach2010-11-151-0/+2
| | | | llvm-svn: 119180
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-5/+5
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* Add *_ldst_mult multiclasses to the ARM back-end. These will be used in theBill Wendling2010-11-131-0/+12
| | | | | | | future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
* More ARM load/store indexed refactoring. Also fix an incorrect IndexModeJim Grosbach2010-11-131-42/+13
| | | | | | flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
* Refactor to parameterize some ARM load/store encoding patterns. PreparatoryJim Grosbach2010-11-121-74/+12
| | | | | | | to splitting the load/store pre/post indexed instructions into [r, r] and [r, imm] forms. llvm-svn: 118925
* Add some missing isel predicates on def : pat patterns to avoid generating ↵Evan Cheng2010-11-121-27/+0
| | | | | | VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. llvm-svn: 118922
* Kill more unused stuff.Jim Grosbach2010-11-121-43/+0
| | | | llvm-svn: 118921
* Remove unused class.Jim Grosbach2010-11-121-8/+0
| | | | llvm-svn: 118919
* Encoding for ARM LDRSB instructions.Jim Grosbach2010-11-121-7/+12
| | | | llvm-svn: 118905
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-111-0/+2
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-111-0/+2
| | | | llvm-svn: 118843
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-111-0/+1
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-111-7/+13
| | | | llvm-svn: 118794
* Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.Jim Grosbach2010-11-111-14/+24
| | | | llvm-svn: 118767
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