summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMInstrFormats.td
Commit message (Collapse)AuthorAgeFilesLines
...
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-0/+14
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson2011-08-041-0/+21
| | | | llvm-svn: 136942
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-38/+7
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-3/+22
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* ARM fix for LDREX source register encoding.Jim Grosbach2011-07-261-2/+2
| | | | | | rdar://9842203 llvm-svn: 136102
* ARM assembly parsing and encoding for SWP[B] instructions.Jim Grosbach2011-07-261-3/+3
| | | | llvm-svn: 136098
* Clean up the ARM asm parser a bit.Jim Grosbach2011-07-261-1/+1
| | | | | | | No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. llvm-svn: 136095
* More simple cleanup of ARM asm operand definitions.Jim Grosbach2011-07-251-27/+9
| | | | llvm-svn: 135958
* Make assembly parser method names more consistent.Jim Grosbach2011-07-251-3/+3
| | | | llvm-svn: 135950
* ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2011-07-221-0/+5
| | | | | | | Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-1/+2
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach2011-07-211-0/+10
| | | | llvm-svn: 135682
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-201-2/+6
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Tidy up a bit.Jim Grosbach2011-07-201-0/+3
| | | | | | | Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename them to be a bit more descriptive that they're for the PKH instructions. llvm-svn: 135617
* ARM: Tidy up representation of PKH instruction.Jim Grosbach2011-07-201-2/+2
| | | | | | | | | The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't be also encoded as part of the shift value immediate. Otherwise we're able to represent invalid instructions, plus it needlessly complicates the representation. Preparatory work for asm parsing of these instructions. llvm-svn: 135616
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-191-2/+11
| | | | | | decoders for ARM. llvm-svn: 135524
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-131-110/+99
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* Parameterize away the ARM T1Cop class.Jim Grosbach2011-07-131-7/+2
| | | | llvm-svn: 135082
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-131-8/+6
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-081-0/+19
| | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
* Mark ARM pseudo-instructions as isPseudo.Jim Grosbach2011-07-061-5/+3
| | | | | | | | | | This allows us to remove the (bogus and unneeded) encoding information from the pseudo-instruction class definitions. All of the pseudos that haven't been converted yet and still need encoding information instance from the normal instruction classes and explicitly set isCodeGenOnly, and so are distinct from this change. llvm-svn: 134540
* Make the branch encoding for tBcc more obvious that it's a 4-byte opcodeEric Christopher2011-05-271-0/+4
| | | | | | followed by a conditional and imm8. llvm-svn: 132179
* 80 columns.Jim Grosbach2011-05-191-9/+12
| | | | llvm-svn: 131649
* Add a few ARM coprocessor intrinsics. Testcases includedBruno Cardoso Lopes2011-05-031-0/+8
| | | | llvm-svn: 130763
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-0/+2
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-041-0/+41
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-0/+18
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-6/+6
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-6/+6
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-311-6/+6
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* Somehow we managed to forget to encode the lane index for a large swathe of ↵Owen Anderson2011-03-301-1/+50
| | | | | | NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. llvm-svn: 128587
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-301-6/+6
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-2/+2
| | | | llvm-svn: 128236
* Remove some dead patterns.Jim Grosbach2011-03-141-10/+0
| | | | llvm-svn: 127601
* Pseudo-instructions are codegenonly by definition.Jim Grosbach2011-03-101-0/+1
| | | | llvm-svn: 127420
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-071-13/+18
| | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. llvm-svn: 127193
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+16
| | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723
* Change VFPNeonA8 definition to make the code easier to read.Evan Cheng2011-02-231-1/+1
| | | | llvm-svn: 126298
* VFP single precision arith instructions can go down to NEON pipeline, but on ↵Evan Cheng2011-02-221-3/+4
| | | | | | Cortex-A8 only. llvm-svn: 126238
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-0/+7
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Some single precision VFP instructions may be executed on NEON pipeline, but ↵Evan Cheng2011-02-161-4/+4
| | | | | | not double precision ones. llvm-svn: 125624
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-0/+16
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-121-1/+1
| | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. llvm-svn: 125426
* Add support for parsing dmb/dsb instructionsBruno Cardoso Lopes2011-02-071-0/+6
| | | | llvm-svn: 125055
* Add mcr*2 and mr*c2 support to thumb2 targetsBruno Cardoso Lopes2011-01-201-0/+6
| | | | llvm-svn: 123919
* Add mcr* and mr*c support to thumb targetsBruno Cardoso Lopes2011-01-201-0/+7
| | | | llvm-svn: 123917
* Add a FIXME.Jim Grosbach2011-01-181-0/+1
| | | | llvm-svn: 123769
* The new t2LEApcrel* pseudo instructions need the size specified.Jim Grosbach2010-12-151-0/+7
| | | | | | rdar://8768390 llvm-svn: 121876
* Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and ↵Owen Anderson2010-12-101-0/+1
| | | | | | friends. llvm-svn: 121585
* Tidy up.Jim Grosbach2010-12-101-11/+8
| | | | llvm-svn: 121522
OpenPOWER on IntegriCloud