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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher2015-03-121-1/+1
* Silencing an "enumeral and non-enumeral type in conditional expression" warni...Aaron Ballman2015-03-121-1/+1
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-111-3/+3
* ARM: simplify and extend byval handlingTim Northover2015-03-111-216/+103
* Remove the remaining uses of abs64 and nuke it.Benjamin Kramer2015-03-091-3/+3
* Make constant arrays that are passed to functions as const.Benjamin Kramer2015-03-071-7/+5
* [ARM] Enable vector extload combine for legal types.Ahmed Bougacha2015-03-051-0/+22
* Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how ...JF Bastien2015-03-041-2/+5
* Remove MCStreamer.h include from MCContext.h and explictly include it where n...Pete Cooper2015-03-041-0/+1
* getRegForInlineAsmConstraint wants to use TargetRegisterInfo forEric Christopher2015-02-261-2/+3
* Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.Eric Christopher2015-02-261-4/+5
* ARM: treat [N x i32] and [N x i64] as AAPCS composite typesTim Northover2015-02-241-4/+8
* Rewrite the global merge pass to be subprogram agnostic for now.Eric Christopher2015-02-231-6/+0
* CodeGen: convert CCState interface to using ArrayRefsTim Northover2015-02-211-9/+6
* [ARM] Re-re-apply VLD1/VST1 base-update combine.Ahmed Bougacha2015-02-191-14/+117
* [ARM] Minor cleanup to CombineBaseUpdate. NFC.Ahmed Bougacha2015-02-191-20/+22
* [CodeGen] Use ArrayRef instead of std::vector&. NFC.Ahmed Bougacha2015-02-191-1/+1
* AArch64: Safely handle the incoming sret call argument.Andrew Trick2015-02-161-3/+8
* ARM: Canonicalize access to function attributes, NFCDuncan P. N. Exon Smith2015-02-141-9/+4
* MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line wit...Benjamin Kramer2015-02-121-5/+1
* ARM & AArch64: teach LowerVSETCC that output type size may differ from input.Tim Northover2015-02-081-13/+16
* Reverting VLD1/VST1 base-updating/post-incrementing combiningRenato Golin2015-02-041-102/+14
* Remove getSubtargetImpl from ARMISelLowering and cache theEric Christopher2015-01-291-31/+19
* This patch fixes issue with lowering below mentioned pattern :-Jyoti Allur2015-01-231-7/+10
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-10/+16
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-071-17/+12
* ARM: permit tail calls to weak externals on COFFSaleem Abdulrasool2015-01-031-1/+3
* [ARM] Don't break alignment when combining base updates into load/stores.Ahmed Bougacha2014-12-231-2/+47
* Fixing -Wsign-compare warnings; NFC.Aaron Ballman2014-12-161-1/+2
* [ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanesBradley Smith2014-12-161-3/+5
* Silence more static analyzer warnings.Michael Ilseman2014-12-151-1/+3
* Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."Ahmed Bougacha2014-12-131-6/+40
* Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."Renato Golin2014-12-131-38/+6
* [ARM] Combine base-updating/post-incrementing vector load/stores.Ahmed Bougacha2014-12-101-6/+38
* [ARM] Factor out base-updating VLD/VST combiner function. NFC.Ahmed Bougacha2014-12-091-6/+15
* [ARM] Move the store combiner function down. NFC.Ahmed Bougacha2014-12-091-141/+143
* Both of these subtargets have functions that check whether orEric Christopher2014-12-051-1/+1
* Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'Craig Topper2014-11-211-19/+12
* Fix more instances of -Wsentinel on Windows with s/NULL/nullptr/Reid Kleckner2014-11-201-2/+2
* Update SetVector to rely on the underlying set's insert to return a pair<iter...David Blaikie2014-11-191-1/+1
* We can get the TLOF from the TargetMachine - so constructor no longer require...Aditya Nandakumar2014-11-131-1/+1
* This patch changes the ownership of TLOF from TargetLoweringBase to TargetMac...Aditya Nandakumar2014-11-131-9/+1
* [ARM, inline-asm] Fix ARMTargetLowering::getRegForInlineAsmConstraint to returnAkira Hatanaka2014-11-031-0/+2
* Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC.Daniel Sanders2014-11-011-3/+3
* [CodeGenPrepare] Move extractelement close to store if they can be combined.Quentin Colombet2014-10-311-0/+29
* [ARM] Select VMAXNM and VMINNM regardless of operand orderOliver Stannard2014-10-271-6/+12
* Do not emit intermediate register for zero FP immediateRenato Golin2014-10-231-0/+12
* ARM: rework Thumb1 frame index rewritingTim Northover2014-10-201-3/+3
* Use triple's isiOS() and isOSDarwin() methods.Bob Wilson2014-10-091-1/+1
* constify TargetMachine argument.Eric Christopher2014-10-031-1/+1
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