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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-121-4/+7
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* isLegalICmpImmediate should take a signed integer; code clean up.Evan Cheng2009-11-121-31/+22
| | | | llvm-svn: 86964
* Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be ↵Evan Cheng2009-11-111-0/+12
| | | | | | folded into target icmp instructions. llvm-svn: 86858
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-19/+19
| | | | llvm-svn: 86494
* Remove ARMPCLabelIndex from ARMISelLowering. Use ↵Evan Cheng2009-11-061-10/+33
| | | | | | ARMFunctionInfo::createConstPoolEntryUId() instead. llvm-svn: 86294
* Revert previous change to a comment. The BlockAddresses go in theBob Wilson2009-11-031-6/+6
| | | | | | constant pool so they don't get wrapped separately. llvm-svn: 85844
* Put BlockAddresses into ARM constant pools.Bob Wilson2009-11-021-2/+19
| | | | llvm-svn: 85824
* Handle splats of undefs properly. This includes the testcase for PR5364 as well.Anton Korobeynikov2009-11-021-0/+3
| | | | llvm-svn: 85767
* Expand 64-bit logical shift right inlineJim Grosbach2009-10-311-4/+7
| | | | llvm-svn: 85687
* Expand 64-bit arithmetic shift right inlineJim Grosbach2009-10-311-1/+36
| | | | llvm-svn: 85685
* Expand 64 bit left shift inline rather than using the libcall. For now, thisJim Grosbach2009-10-311-1/+36
| | | | | | | is unconditional. Making it still use the libcall when optimizing for size would be a good adjustment. llvm-svn: 85675
* It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to ↵Evan Cheng2009-10-311-14/+28
| | | | | | enable more machine licm. More changes coming. llvm-svn: 85643
* Fix a comment.Bob Wilson2009-10-301-1/+1
| | | | llvm-svn: 85610
* This fixes functions likeRafael Espindola2009-10-301-2/+1
| | | | | | | | | | | void f (int a1, int a2, int a3, int a4, int a5,...) In ARMTargetLowering::LowerFormalArguments if the function has 4 or more regular arguments we used to set VarArgsFrameIndex using an offset of 0, which is only correct if the function has exactly 4 regular arguments. llvm-svn: 85590
* Add ARM codegen for indirect branches.Bob Wilson2009-10-301-6/+15
| | | | | | clang/test/CodeGen/indirect-goto.c runs! (unoptimized) llvm-svn: 85577
* Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.Evan Cheng2009-10-281-0/+3
| | | | llvm-svn: 85381
* Use fconsts and fconstd to materialize small fp constants.Evan Cheng2009-10-281-0/+57
| | | | llvm-svn: 85362
* Most of the NEON shuffle instructions do not support 64-bit element types.Bob Wilson2009-10-211-3/+18
| | | | llvm-svn: 84785
* Match more patterns to movt.Evan Cheng2009-10-211-1/+0
| | | | llvm-svn: 84751
* Random #include pruning.Benjamin Kramer2009-10-201-1/+2
| | | | llvm-svn: 84632
* Revert svn r80498 and replace it with a different solution. The only problemBob Wilson2009-10-151-12/+4
| | | | | | | | | | | | | | I can see with the original code was that I forgot that this runs after type legalization and hence the result type will always be i32. (Custom legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with 8- and 16-bit elements.) Regarding the FIXME comment: any information about sign and zero-extension should be captured by separate extension operations. The DAG combiner should handle those to produce either VGETLANEu or VGETLANEs, and that seems to be working now. If there are cases that we're missing, let me know. llvm-svn: 84218
* More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsicsBob Wilson2009-10-131-54/+0
| | | | | | | by creating TargetConstants during instruction selection instead of during legalization. llvm-svn: 84042
* NEON VLD/VST are now fully implemented. For operations that expand toBob Wilson2009-10-131-48/+2
| | | | | | | multiple instructions, the expansion is done during selection so there is no need to do anything special during legalization. llvm-svn: 84036
* Add PseudoSourceValues for constpool stuff on ELF (Darwin should use ↵Anton Korobeynikov2009-10-071-4/+8
| | | | | | | | something similar) and register spills. llvm-svn: 83435
* getFunctionAlignment should return log2 alignment.Evan Cheng2009-10-021-1/+1
| | | | llvm-svn: 83242
* ARM does not support offset folding (yet). Disable it for now.Anton Korobeynikov2009-09-231-0/+6
| | | | | | This fixes PR5031. Unfortunately, there is no small testcase :( llvm-svn: 82643
* Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic ↵Evan Cheng2009-09-191-4/+7
| | | | | | blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks. llvm-svn: 82311
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-1/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Expand vector floating-point conversions not supported by NEON.Bob Wilson2009-09-161-0/+6
| | | | llvm-svn: 82074
* Expand some more vector operations not supported by Neon.Bob Wilson2009-09-161-0/+6
| | | | llvm-svn: 81969
* Neon does not support vector divide or remainder. Expand them.Bob Wilson2009-09-161-0/+8
| | | | llvm-svn: 81966
* Expand all v2f64 arithmetic operations for Neon.Bob Wilson2009-09-151-0/+27
| | | | | | | Radar 7200803. (This should also fix the SingleSource/UnitTests/Vector/sumarray-dbl test.) llvm-svn: 81959
* Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.Bob Wilson2009-09-091-12/+5
| | | | | | See the bug report for details. llvm-svn: 81397
* Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.Anton Korobeynikov2009-09-081-13/+23
| | | | llvm-svn: 81262
* Reference to hidden symbols do not have to go through non-lazy pointer in ↵Evan Cheng2009-09-031-1/+1
| | | | | | non-pic mode. rdar://7187172. llvm-svn: 80904
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-021-5/+5
| | | | llvm-svn: 80773
* Add support for generating code for vst{234}lane intrinsics.Bob Wilson2009-09-011-0/+26
| | | | llvm-svn: 80707
* Generate code for vld{234}_lane intrinsics.Bob Wilson2009-09-011-0/+26
| | | | llvm-svn: 80656
* Clean up LSDA name generation and use for SJLJ exception handling. ThisJim Grosbach2009-09-011-14/+8
| | | | | | | | | | | makes an eggregious hack somewhat more palatable. Bringing the LSDA forward and making it a GV available for reference would be even better, but is beyond the scope of what I'm looking to solve at this point. Objective C++ code could generate function names that broke the previous scheme. This fixes that. llvm-svn: 80649
* EXTRACT_VECTOR_ELEMENT can have result type different from element type.Anton Korobeynikov2009-08-301-3/+10
| | | | | | Remove the assertion and generalize the code for ARM NEON stuff. llvm-svn: 80498
* Do not assert on too wide splats we don't support.Anton Korobeynikov2009-08-291-4/+6
| | | | llvm-svn: 80409
* Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a ↵Evan Cheng2009-08-281-32/+14
| | | | | | bunch of nasty code in ARM asm printer. llvm-svn: 80404
* Hopefully the final missing part :(Anton Korobeynikov2009-08-271-12/+0
| | | | | | scalar_to_vector is fully legal now llvm-svn: 80251
* Transform float scalar_to_vector into subreg accesses.Anton Korobeynikov2009-08-271-1/+7
| | | | | | No idea whether this is profitable or not. llvm-svn: 80245
* Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.Bob Wilson2009-08-261-31/+18
| | | | | | | | The instructions can be selected directly from the intrinsics. We will need to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but those are not yet implemented. llvm-svn: 80117
* Expand scalar_to_vector - we don't have any isel logic for it nowAnton Korobeynikov2009-08-261-1/+1
| | | | llvm-svn: 80107
* Make x86 test actually test x86 code generation. Fix the Eli Friedman2009-08-221-2/+5
| | | | | | | construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. llvm-svn: 79719
* Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,Bob Wilson2009-08-211-6/+72
| | | | | | now using shuffles instead of intrinsics. llvm-svn: 79673
* Fix some typos and use type-based isel for VZIP/VUZP/VTRNAnton Korobeynikov2009-08-211-17/+8
| | | | llvm-svn: 79625
* Add lowering of ARM 4-element shuffles to multiple instructios via ↵Anton Korobeynikov2009-08-211-8/+123
| | | | | | perfectshuffle-generated table. llvm-svn: 79624
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