| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -3/+3 |
| * | Remove warning: 'c0' may be used uninitialized in this function. | Chad Rosier | 2011-06-28 | 1 | -1/+2 |
| * | The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) | Chad Rosier | 2011-06-24 | 1 | -1/+104 |
| * | Handle the memory-ness of all U+ ARM constraints. | Eric Christopher | 2011-06-21 | 1 | -3/+6 |
| * | Remove unused but set variables. | Benjamin Kramer | 2011-06-18 | 1 | -1/+0 |
| * | Mark ldrexd/strexd w/ volatile memory by default | Bruno Cardoso Lopes | 2011-06-16 | 1 | -2/+2 |
| * | Revision r128665 added an optimization to make use of NEON multiplier | Chad Rosier | 2011-06-16 | 1 | -1/+1 |
| * | A minor simplification: no functional change. | Bob Wilson | 2011-06-15 | 1 | -7/+4 |
| * | PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff | Evan Cheng | 2011-06-15 | 1 | -4/+7 |
| * | Add an optimization that looks for a specific pair-wise add pattern and gener... | Tanya Lattner | 2011-06-14 | 1 | -5/+106 |
| * | Add one more argument to the prefetch intrinsic to indicate whether it's a data | Bruno Cardoso Lopes | 2011-06-14 | 1 | -3/+4 |
| * | Provide an ARMCCState subclass of CCState so that ARM clients will always set | Cameron Zwarich | 2011-06-10 | 1 | -17/+29 |
| * | A CCState was being created without setting whether it is in the Call or Prol... | Cameron Zwarich | 2011-06-09 | 1 | -0/+1 |
| * | Add a parameter to CCState so that it can access the MachineFunction. | Eric Christopher | 2011-06-08 | 1 | -16/+16 |
| * | Make the Uv constraint a memory operand. This doesn't solve the | Eric Christopher | 2011-06-03 | 1 | -0/+3 |
| * | Have LowerOperandForConstraint handle multiple character constraints. | Eric Christopher | 2011-06-02 | 1 | -3/+7 |
| * | On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. | John McCall | 2011-05-29 | 1 | -0/+1 |
| * | I didn't mean to commit these residues of a personal project. | John McCall | 2011-05-29 | 1 | -1/+0 |
| * | On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. | John McCall | 2011-05-29 | 1 | -0/+1 |
| * | Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs | Bruno Cardoso Lopes | 2011-05-28 | 1 | -0/+22 |
| * | Fix the remaining atomic intrinsics to use the right register classes on Thumb2, | Cameron Zwarich | 2011-05-27 | 1 | -10/+23 |
| * | Don't use movw / movt for iOS static codegen for now to workaround some tools... | Evan Cheng | 2011-05-27 | 1 | -1/+2 |
| * | RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ... | Renato Golin | 2011-05-22 | 1 | -0/+6 |
| * | Revert accidental commit. | Evan Cheng | 2011-05-20 | 1 | -1/+1 |
| * | Revert r131664 and fix it in instcombine instead. rdar://9467055 | Evan Cheng | 2011-05-20 | 1 | -1/+1 |
| * | Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for t... | Mon P Wang | 2011-05-19 | 1 | -7/+7 |
| * | Handle perfect shuffle case that generates a vrev for vectors of floats. | Tanya Lattner | 2011-05-18 | 1 | -1/+2 |
| * | Revise r131553. Just use the type of the input node and forgo the bitcast. rd... | Evan Cheng | 2011-05-18 | 1 | -4/+3 |
| * | Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ty... | Evan Cheng | 2011-05-18 | 1 | -1/+3 |
| * | In r131488 I misunderstood how VREV works. It splits the vector in half and s... | Tanya Lattner | 2011-05-18 | 1 | -1/+9 |
| * | Fix typo. | Cameron Zwarich | 2011-05-18 | 1 | -4/+4 |
| * | Fix more of PR8825 by correctly using rGPR registers when lowering atomic | Cameron Zwarich | 2011-05-18 | 1 | -2/+11 |
| * | Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp | Bill Wendling | 2011-05-11 | 1 | -1/+1 |
| * | Make the logic for determining function alignment more explicit. No function... | Eli Friedman | 2011-05-06 | 1 | -5/+2 |
| * | Temporarily disable use of divmod compiler-rt functions for iOS. | Bob Wilson | 2011-05-03 | 1 | -6/+0 |
| * | Add an unfolded offset field to LSR's Formula record. This is used to | Dan Gohman | 2011-05-03 | 1 | -0/+8 |
| * | 80-col. | Eric Christopher | 2011-04-29 | 1 | -8/+9 |
| * | ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. | Jim Grosbach | 2011-04-26 | 1 | -0/+143 |
| * | Thumb2 and ARM add/subtract with carry fixes. | Andrew Trick | 2011-04-23 | 1 | -66/+73 |
| * | Remove -use-divmod-libcall. Let targets opt in when they are available. | Evan Cheng | 2011-04-20 | 1 | -1/+2 |
| * | Excise unintended hunk in 129858. <rdar://problem/7662569> | Stuart Hastings | 2011-04-20 | 1 | -5/+0 |
| * | ARM byval support. Will be enabled by another patch to the FE. <rdar://prob... | Stuart Hastings | 2011-04-20 | 1 | -78/+164 |
| * | Remove some duplicate op action entries and reorganize. | Eric Christopher | 2011-04-19 | 1 | -8/+5 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -2/+2 |
| * | Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't | Evan Cheng | 2011-04-15 | 1 | -1/+4 |
| * | Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. | Cameron Zwarich | 2011-04-13 | 1 | -1/+1 |
| * | Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM | Cameron Zwarich | 2011-04-12 | 1 | -2/+22 |
| * | Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is... | Evan Cheng | 2011-04-08 | 1 | -23/+1 |
| * | Add option to emit @llvm.trap as a function call instead of a trap instructio... | Evan Cheng | 2011-04-07 | 1 | -1/+23 |
| * | Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector... | Tanya Lattner | 2011-04-07 | 1 | -0/+6 |
